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#ifndef KERN_sparc64_BARRIER_H_
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#ifndef KERN_sparc64_BARRIER_H_
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#define KERN_sparc64_BARRIER_H_
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#define KERN_sparc64_BARRIER_H_
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/*
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/*
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 * We assume TSO memory model in which only reads can pass earlier stores
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 * Our critical section barriers are prepared for the weakest RMO memory model.
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 * (but not earlier reads). Therefore, CS_ENTER_BARRIER() and CS_LEAVE_BARRIER()
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 * can be empty.
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 */
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 */
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#define CS_ENTER_BARRIER()  __asm__ volatile ("" ::: "memory")
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#define CS_ENTER_BARRIER()              \
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    __asm__ volatile (              \
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        "membar #LoadLoad | #LoadStore\n"   \
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        ::: "memory"                \
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    )
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#define CS_LEAVE_BARRIER()  __asm__ volatile ("" ::: "memory")
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#define CS_LEAVE_BARRIER()              \
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    __asm__ volatile (              \
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        "membar #StoreStore\n"          \
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        "membar #LoadStore\n"           \
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        ::: "memory"                \
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    )
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#define memory_barrier()    \
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#define memory_barrier()    __asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
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    __asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
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#define read_barrier()      \
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#define read_barrier()      __asm__ volatile ("membar #LoadLoad\n" ::: "memory")
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    __asm__ volatile ("membar #LoadLoad\n" ::: "memory")
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#define write_barrier()     \
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#define write_barrier()     __asm__ volatile ("membar #StoreStore\n" ::: "memory")
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    __asm__ volatile ("membar #StoreStore\n" ::: "memory")
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/** Flush Instruction Memory instruction. */
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/** Flush Instruction Memory instruction. */
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static inline void flush(void)
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static inline void flush(void)
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{
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{
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    /*
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    /*