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| 49 | static inline void flush(void) |
49 | static inline void flush(void) |
| 50 | { |
50 | { |
| 51 | /* |
51 | /* |
| 52 | * The FLUSH instruction takes address parameter. |
52 | * The FLUSH instruction takes address parameter. |
| 53 | * As such, it may trap if the address is not found in DTLB. |
53 | * As such, it may trap if the address is not found in DTLB. |
| - | 54 | * |
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| 54 | * However, JPS1 implementations are free to ignore the trap. |
55 | * The entire kernel text is mapped by a locked ITLB and |
| - | 56 | * DTLB entries. Therefore, when this function is called, |
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| - | 57 | * the %o7 register will always be in the range mapped by |
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| - | 58 | * DTLB. |
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| 55 | */ |
59 | */ |
| 56 | 60 | ||
| 57 | __asm__ volatile ("flush %0\n" :: "r" (0x400000)); |
61 | __asm__ volatile ("flush %o7\n"); |
| 58 | } |
62 | } |
| 59 | 63 | ||
| 60 | /** Memory Barrier instruction. */ |
64 | /** Memory Barrier instruction. */ |
| 61 | static inline void membar(void) |
65 | static inline void membar(void) |
| 62 | { |
66 | { |