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| Rev 2071 | Rev 2082 | ||
|---|---|---|---|
| Line 55... | Line 55... | ||
| 55 | do { |
55 | do { |
| 56 | volatile uintptr_t x = (uint64_t) &val->count; |
56 | volatile uintptr_t x = (uint64_t) &val->count; |
| 57 | 57 | ||
| 58 | a = *((uint64_t *) x); |
58 | a = *((uint64_t *) x); |
| 59 | b = a + i; |
59 | b = a + i; |
| 60 | __asm__ volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)), "+r" (b) : "r" (a)); |
60 | asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)), "+r" (b) : "r" (a)); |
| 61 | } while (a != b); |
61 | } while (a != b); |
| 62 | 62 | ||
| 63 | return a; |
63 | return a; |
| 64 | } |
64 | } |
| 65 | 65 | ||
| Line 96... | Line 96... | ||
| 96 | static inline long test_and_set(atomic_t *val) |
96 | static inline long test_and_set(atomic_t *val) |
| 97 | { |
97 | { |
| 98 | uint64_t v = 1; |
98 | uint64_t v = 1; |
| 99 | volatile uintptr_t x = (uint64_t) &val->count; |
99 | volatile uintptr_t x = (uint64_t) &val->count; |
| 100 | 100 | ||
| 101 | __asm__ volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), "+r" (v) : "r" (0)); |
101 | asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), "+r" (v) : "r" (0)); |
| 102 | 102 | ||
| 103 | return v; |
103 | return v; |
| 104 | } |
104 | } |
| 105 | 105 | ||
| 106 | static inline void atomic_lock_arch(atomic_t *val) |
106 | static inline void atomic_lock_arch(atomic_t *val) |
| Line 108... | Line 108... | ||
| 108 | uint64_t tmp1 = 1; |
108 | uint64_t tmp1 = 1; |
| 109 | uint64_t tmp2; |
109 | uint64_t tmp2; |
| 110 | 110 | ||
| 111 | volatile uintptr_t x = (uint64_t) &val->count; |
111 | volatile uintptr_t x = (uint64_t) &val->count; |
| 112 | 112 | ||
| 113 | __asm__ volatile ( |
113 | asm volatile ( |
| 114 | "0:\n" |
114 | "0:\n" |
| 115 | "casx %0, %3, %1\n" |
115 | "casx %0, %3, %1\n" |
| 116 | "brz %1, 2f\n" |
116 | "brz %1, 2f\n" |
| 117 | "nop\n" |
117 | "nop\n" |
| 118 | "1:\n" |
118 | "1:\n" |