WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/include/asm.h



 */
static inline uint64_t pstate_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Processor State register.
 *
 * @param v New value of PSTATE register.
 */
static inline void pstate_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
}
 
/** Read TICK_compare Register.
 *
 * @return Value of TICK_comapre register.
 */
static inline uint64_t tick_compare_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK_compare Register.
 *
 * @param v New value of TICK_comapre register.
 */
static inline void tick_compare_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
}
 
/** Read TICK Register.
 *
 * @return Value of TICK register.
 */
static inline uint64_t tick_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK Register.
 *
 * @param v New value of TICK register.
 */
static inline void tick_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
}
 
/** Read FPRS Register.
 *
 * @return Value of FPRS register.
 */
static inline uint64_t fprs_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%fprs, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write FPRS Register.
 *
 * @param v New value of FPRS register.
 */
static inline void fprs_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
}
 
/** Read SOFTINT Register.
 *
 * @return Value of SOFTINT register.
 */
static inline uint64_t softint_read(void)
{
    uint64_t v;
 
    asm volatile ("rd %%softint, %0\n" : "=r" (v));
 
    return v;
}
 
/** Write SOFTINT Register.
 *
 * @param v New value of SOFTINT register.
 */
static inline void softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
}
 
/** Write CLEAR_SOFTINT Register.
 *
 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
 *
 * @param v New value of CLEAR_SOFTINT register.
 */
static inline void clear_softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
}
 
/** Write SET_SOFTINT Register.
 *
 * Bits set in SET_SOFTINT register will be set in SOFTINT register.
 *
 * @param v New value of SET_SOFTINT register.
 */
static inline void set_softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous

 */
static inline uintptr_t get_stack_base(void)
{
    uintptr_t unbiased_sp;
   
    asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
   
    return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
}
 
/** Read Version Register.

 */
static inline uint64_t ver_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Program Counter register.

 */
static inline uint64_t tpc_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Level register.

 */
static inline uint64_t tl_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Base Address register.

 */
static inline uint64_t tba_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Trap Base Address register.
 *
 * @param v New value of TBA.
 */
static inline void tba_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
}
 
/** Load uint64_t from alternate space.
 *
 * @param asi ASI determining the alternate space.

 */
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
{
    uint64_t v;
   
    asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
   
    return v;
}
 
/** Store uint64_t to alternate space.

 * @param va Virtual address within the ASI.
 * @param v Value to be written.
 */
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
{
    asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
}
 
/** Flush all valid register windows to memory. */
static inline void flushw(void)
{
    asm volatile ("flushw\n");
}
 
/** Switch to nucleus by setting TL to 1. */
static inline void nucleus_enter(void)
{
    asm volatile ("wrpr %g0, 1, %tl\n");
}
 
/** Switch from nucleus by setting TL to 0. */
static inline void nucleus_leave(void)
{
    asm volatile ("wrpr %g0, %g0, %tl\n");
}
 
/** Read UPA_CONFIG register.
 *
 * @return Value of the UPA_CONFIG register.

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/include/asm.h – Rev 2071 → 2082

Rev 2071		Rev 2082
Line 49...		Line 49...
49	*/	49	*/
50	static inline uint64_t pstate_read(void)	50	static inline uint64_t pstate_read(void)
51	{	51	{
52	uint64_t v;	52	uint64_t v;
53		53
54	__asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));	54	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
55		55
56	return v;	56	return v;
57	}	57	}
58		58
59	/** Write Processor State register.	59	/** Write Processor State register.
60	*	60	*
61	* @param v New value of PSTATE register.	61	* @param v New value of PSTATE register.
62	*/	62	*/
63	static inline void pstate_write(uint64_t v)	63	static inline void pstate_write(uint64_t v)
64	{	64	{
65	__asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));	65	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
66	}	66	}
67		67
68	/** Read TICK_compare Register.	68	/** Read TICK_compare Register.
69	*	69	*
70	* @return Value of TICK_comapre register.	70	* @return Value of TICK_comapre register.
71	*/	71	*/
72	static inline uint64_t tick_compare_read(void)	72	static inline uint64_t tick_compare_read(void)
73	{	73	{
74	uint64_t v;	74	uint64_t v;
75		75
76	__asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));	76	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
77		77
78	return v;	78	return v;
79	}	79	}
80		80
81	/** Write TICK_compare Register.	81	/** Write TICK_compare Register.
82	*	82	*
83	* @param v New value of TICK_comapre register.	83	* @param v New value of TICK_comapre register.
84	*/	84	*/
85	static inline void tick_compare_write(uint64_t v)	85	static inline void tick_compare_write(uint64_t v)
86	{	86	{
87	__asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));	87	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
88	}	88	}
89		89
90	/** Read TICK Register.	90	/** Read TICK Register.
91	*	91	*
92	* @return Value of TICK register.	92	* @return Value of TICK register.
93	*/	93	*/
94	static inline uint64_t tick_read(void)	94	static inline uint64_t tick_read(void)
95	{	95	{
96	uint64_t v;	96	uint64_t v;
97		97
98	__asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));	98	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
99		99
100	return v;	100	return v;
101	}	101	}
102		102
103	/** Write TICK Register.	103	/** Write TICK Register.
104	*	104	*
105	* @param v New value of TICK register.	105	* @param v New value of TICK register.
106	*/	106	*/
107	static inline void tick_write(uint64_t v)	107	static inline void tick_write(uint64_t v)
108	{	108	{
109	__asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));	109	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
110	}	110	}
111		111
112	/** Read FPRS Register.	112	/** Read FPRS Register.
113	*	113	*
114	* @return Value of FPRS register.	114	* @return Value of FPRS register.
115	*/	115	*/
116	static inline uint64_t fprs_read(void)	116	static inline uint64_t fprs_read(void)
117	{	117	{
118	uint64_t v;	118	uint64_t v;
119		119
120	__asm__ volatile ("rd %%fprs, %0\n" : "=r" (v));	120	asm volatile ("rd %%fprs, %0\n" : "=r" (v));
121		121
122	return v;	122	return v;
123	}	123	}
124		124
125	/** Write FPRS Register.	125	/** Write FPRS Register.
126	*	126	*
127	* @param v New value of FPRS register.	127	* @param v New value of FPRS register.
128	*/	128	*/
129	static inline void fprs_write(uint64_t v)	129	static inline void fprs_write(uint64_t v)
130	{	130	{
131	__asm__ volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));	131	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
132	}	132	}
133		133
134	/** Read SOFTINT Register.	134	/** Read SOFTINT Register.
135	*	135	*
136	* @return Value of SOFTINT register.	136	* @return Value of SOFTINT register.
137	*/	137	*/
138	static inline uint64_t softint_read(void)	138	static inline uint64_t softint_read(void)
139	{	139	{
140	uint64_t v;	140	uint64_t v;
141		141
142	__asm__ volatile ("rd %%softint, %0\n" : "=r" (v));	142	asm volatile ("rd %%softint, %0\n" : "=r" (v));
143		143
144	return v;	144	return v;
145	}	145	}
146		146
147	/** Write SOFTINT Register.	147	/** Write SOFTINT Register.
148	*	148	*
149	* @param v New value of SOFTINT register.	149	* @param v New value of SOFTINT register.
150	*/	150	*/
151	static inline void softint_write(uint64_t v)	151	static inline void softint_write(uint64_t v)
152	{	152	{
153	__asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));	153	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
154	}	154	}
155		155
156	/** Write CLEAR_SOFTINT Register.	156	/** Write CLEAR_SOFTINT Register.
157	*	157	*
158	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.	158	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
159	*	159	*
160	* @param v New value of CLEAR_SOFTINT register.	160	* @param v New value of CLEAR_SOFTINT register.
161	*/	161	*/
162	static inline void clear_softint_write(uint64_t v)	162	static inline void clear_softint_write(uint64_t v)
163	{	163	{
164	__asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));	164	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
165	}	165	}
166		166
167	/** Write SET_SOFTINT Register.	167	/** Write SET_SOFTINT Register.
168	*	168	*
169	* Bits set in SET_SOFTINT register will be set in SOFTINT register.	169	* Bits set in SET_SOFTINT register will be set in SOFTINT register.
170	*	170	*
171	* @param v New value of SET_SOFTINT register.	171	* @param v New value of SET_SOFTINT register.
172	*/	172	*/
173	static inline void set_softint_write(uint64_t v)	173	static inline void set_softint_write(uint64_t v)
174	{	174	{
175	__asm__ volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));	175	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
176	}	176	}
177		177
178	/** Enable interrupts.	178	/** Enable interrupts.
179	*	179	*
180	* Enable interrupts and return previous	180	* Enable interrupts and return previous
Line 245...		Line 245...
245	*/	245	*/
246	static inline uintptr_t get_stack_base(void)	246	static inline uintptr_t get_stack_base(void)
247	{	247	{
248	uintptr_t unbiased_sp;	248	uintptr_t unbiased_sp;
249		249
250	__asm__ volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));	250	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
251		251
252	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);	252	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
253	}	253	}
254		254
255	/** Read Version Register.	255	/** Read Version Register.
Line 258...		Line 258...
258	*/	258	*/
259	static inline uint64_t ver_read(void)	259	static inline uint64_t ver_read(void)
260	{	260	{
261	uint64_t v;	261	uint64_t v;
262		262
263	__asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));	263	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
264		264
265	return v;	265	return v;
266	}	266	}
267		267
268	/** Read Trap Program Counter register.	268	/** Read Trap Program Counter register.
Line 271...		Line 271...
271	*/	271	*/
272	static inline uint64_t tpc_read(void)	272	static inline uint64_t tpc_read(void)
273	{	273	{
274	uint64_t v;	274	uint64_t v;
275		275
276	__asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));	276	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
277		277
278	return v;	278	return v;
279	}	279	}
280		280
281	/** Read Trap Level register.	281	/** Read Trap Level register.
Line 284...		Line 284...
284	*/	284	*/
285	static inline uint64_t tl_read(void)	285	static inline uint64_t tl_read(void)
286	{	286	{
287	uint64_t v;	287	uint64_t v;
288		288
289	__asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v));	289	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
290		290
291	return v;	291	return v;
292	}	292	}
293		293
294	/** Read Trap Base Address register.	294	/** Read Trap Base Address register.
Line 297...		Line 297...
297	*/	297	*/
298	static inline uint64_t tba_read(void)	298	static inline uint64_t tba_read(void)
299	{	299	{
300	uint64_t v;	300	uint64_t v;
301		301
302	__asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));	302	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
303		303
304	return v;	304	return v;
305	}	305	}
306		306
307	/** Write Trap Base Address register.	307	/** Write Trap Base Address register.
308	*	308	*
309	* @param v New value of TBA.	309	* @param v New value of TBA.
310	*/	310	*/
311	static inline void tba_write(uint64_t v)	311	static inline void tba_write(uint64_t v)
312	{	312	{
313	__asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));	313	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
314	}	314	}
315		315
316	/** Load uint64_t from alternate space.	316	/** Load uint64_t from alternate space.
317	*	317	*
318	* @param asi ASI determining the alternate space.	318	* @param asi ASI determining the alternate space.
Line 322...		Line 322...
322	*/	322	*/
323	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)	323	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
324	{	324	{
325	uint64_t v;	325	uint64_t v;
326		326
327	__asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));	327	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
328		328
329	return v;	329	return v;
330	}	330	}
331		331
332	/** Store uint64_t to alternate space.	332	/** Store uint64_t to alternate space.
Line 335...		Line 335...
335	* @param va Virtual address within the ASI.	335	* @param va Virtual address within the ASI.
336	* @param v Value to be written.	336	* @param v Value to be written.
337	*/	337	*/
338	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)	338	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
339	{	339	{
340	__asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");	340	asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
341	}	341	}
342		342
343	/** Flush all valid register windows to memory. */	343	/** Flush all valid register windows to memory. */
344	static inline void flushw(void)	344	static inline void flushw(void)
345	{	345	{
346	__asm__ volatile ("flushw\n");	346	asm volatile ("flushw\n");
347	}	347	}
348		348
349	/** Switch to nucleus by setting TL to 1. */	349	/** Switch to nucleus by setting TL to 1. */
350	static inline void nucleus_enter(void)	350	static inline void nucleus_enter(void)
351	{	351	{
352	__asm__ volatile ("wrpr %g0, 1, %tl\n");	352	asm volatile ("wrpr %g0, 1, %tl\n");
353	}	353	}
354		354
355	/** Switch from nucleus by setting TL to 0. */	355	/** Switch from nucleus by setting TL to 0. */
356	static inline void nucleus_leave(void)	356	static inline void nucleus_leave(void)
357	{	357	{
358	__asm__ volatile ("wrpr %g0, %g0, %tl\n");	358	asm volatile ("wrpr %g0, %g0, %tl\n");
359	}	359	}
360		360
361	/** Read UPA_CONFIG register.	361	/** Read UPA_CONFIG register.
362	*	362	*
363	* @return Value of the UPA_CONFIG register.	363	* @return Value of the UPA_CONFIG register.