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263 | __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v)); |
263 | __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v)); |
264 | 264 | ||
265 | return v; |
265 | return v; |
266 | } |
266 | } |
267 | 267 | ||
268 | /** Read Trap Base Address register. |
268 | /** Read Trap Program Counter register. |
269 | * |
269 | * |
270 | * @return Current value in TBA. |
270 | * @return Current value in TPC. |
271 | */ |
271 | */ |
272 | static inline uint64_t tba_read(void) |
272 | static inline uint64_t tpc_read(void) |
273 | { |
273 | { |
274 | uint64_t v; |
274 | uint64_t v; |
275 | 275 | ||
276 | __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
276 | __asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v)); |
277 | 277 | ||
278 | return v; |
278 | return v; |
279 | } |
279 | } |
280 | 280 | ||
281 | /** Read Trap Program Counter register. |
281 | /** Read Trap Level register. |
282 | * |
282 | * |
283 | * @return Current value in TPC. |
283 | * @return Current value in TL. |
284 | */ |
284 | */ |
285 | static inline uint64_t tpc_read(void) |
285 | static inline uint64_t tl_read(void) |
286 | { |
286 | { |
287 | uint64_t v; |
287 | uint64_t v; |
288 | 288 | ||
289 | __asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v)); |
289 | __asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
290 | 290 | ||
291 | return v; |
291 | return v; |
292 | } |
292 | } |
293 | 293 | ||
294 | /** Read Trap Level register. |
294 | /** Read Trap Base Address register. |
295 | * |
295 | * |
296 | * @return Current value in TL. |
296 | * @return Current value in TBA. |
297 | */ |
297 | */ |
298 | static inline uint64_t tl_read(void) |
298 | static inline uint64_t tba_read(void) |
299 | { |
299 | { |
300 | uint64_t v; |
300 | uint64_t v; |
301 | 301 | ||
302 | __asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
302 | __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
303 | 303 | ||
304 | return v; |
304 | return v; |
305 | } |
305 | } |
306 | 306 | ||
307 | /** Write Trap Base Address register. |
307 | /** Write Trap Base Address register. |