WebSVN – HelenOS – Diff – /trunk/kernel/arch/ppc32/src/mm/tlb.c

     phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);
     phte[base + i].pp = 2; // FIXME
+}
-/** Process Instruction/Data Storage Interrupt
+/** Process Instruction/Data Storage Exception
+ *
- * @param n     Interrupt vector number.
+ * @param n      Exception vector number.
- * @param istate    Interrupted register context.
+ * @param istate Interrupted register context.
+ *
  */
 void pht_refill(int n, istate_t *istate)
+{
     uintptr_t badvaddr;
     page_table_unlock(as, lock);
     pht_refill_fail(badvaddr, istate);
+}
-/** Process Instruction/Data Storage Interrupt in Real Mode
+/** Process Instruction/Data Storage Exception in Real Mode
+ *
- * @param n     Interrupt vector number.
+ * @param n      Exception vector number.
- * @param istate    Interrupted register context.
+ * @param istate Interrupted register context.
+ *
  */
 bool pht_refill_real(int n, istate_t *istate)
+{
     uintptr_t badvaddr;
     return true;
+}
+/** Process ITLB/DTLB Miss Exception in Real Mode
+ *
+ *
+ */
+void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate)
+{
+    uint32_t badvaddr = tlbmiss & 0xfffffffc;
+    uint32_t physmem;
+    asm volatile (
+        "mfsprg3 %0\n"
+        : "=r" (physmem)
+    );
+    if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
+        return; // FIXME
+    ptelo.rpn = KA2PA(badvaddr) >> 12;
+    ptelo.wimg = 0;
+    ptelo.pp = 2; // FIXME
+    uint32_t index = 0;
+    asm volatile (
+        "mtspr 981, %0\n"
+        "mtspr 982, %1\n"
+        "tlbld %2\n"
+        "tlbli %2\n"
+        : "=r" (index)
+        : "r" (ptehi),
+          "r" (ptelo)
+    );
+}
 void tlb_arch_init(void)
+{
     tlb_invalidate_all();
+}

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ppc32/src/mm/tlb.c – Rev 3856 → 3857