WebSVN – HelenOS – Diff – /trunk/kernel/arch/mips32/src/mm/tlb.c

 #include <print.h>
 #include <debug.h>
 #include <align.h>
 #include <interrupt.h>
-static void tlb_refill_fail(istate_t *istate);
+static void tlb_refill_fail(istate_t *);
-static void tlb_invalid_fail(istate_t *istate);
+static void tlb_invalid_fail(istate_t *);
-static void tlb_modified_fail(istate_t *istate);
+static void tlb_modified_fail(istate_t *);
-static pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc);
+static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *);
-/** Initialize TLB
+/** Initialize TLB.
+ *
- * Initialize TLB.
  * Invalidate all entries and mark wired entries.
  */
 void tlb_arch_init(void)
+{
     int i;
      * entries (e.g. mapping kernel stacks in kseg3).
      */
     cp0_wired_write(TLB_WIRED);
+}
-/** Process TLB Refill Exception
+/** Process TLB Refill Exception.
+ *
- * Process TLB Refill Exception.
- *
- * @param istate Interrupted register context.
+ * @param istate    Interrupted register context.
  */
 void tlb_refill(istate_t *istate)
+{
     entry_lo_t lo;
     entry_hi_t hi;
      * Record access to PTE.
      */
     pte->a = 1;
     tlb_prepare_entry_hi(&hi, asid, badvaddr);
-    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
+    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
+        pte->pfn);
     /*
      * New entry is to be inserted into TLB
      */
     cp0_entry_hi_write(hi.value);
-    if ((badvaddr/PAGE_SIZE) % 2 == 0) {
+    if ((badvaddr / PAGE_SIZE) % 2 == 0) {
         cp0_entry_lo0_write(lo.value);
         cp0_entry_lo1_write(0);
+    }
     else {
         cp0_entry_lo0_write(0);
 fail:
     page_table_unlock(AS, true);
     tlb_refill_fail(istate);
+}
-/** Process TLB Invalid Exception
+/** Process TLB Invalid Exception.
- *
- * Process TLB Invalid Exception.
+ *
- * @param istate Interrupted register context.
+ * @param istate    Interrupted register context.
  */
 void tlb_invalid(istate_t *istate)
+{
     tlb_index_t index;
     uintptr_t badvaddr;
     /*
      * Record access to PTE.
      */
     pte->a = 1;
-    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
+    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
+        pte->pfn);
     /*
      * The entry is to be updated in TLB.
      */
-    if ((badvaddr/PAGE_SIZE) % 2 == 0)
+    if ((badvaddr / PAGE_SIZE) % 2 == 0)
         cp0_entry_lo0_write(lo.value);
     else
         cp0_entry_lo1_write(lo.value);
     cp0_pagemask_write(TLB_PAGE_MASK_16K);
     tlbwi();
 fail:
     page_table_unlock(AS, true);
     tlb_invalid_fail(istate);
+}
-/** Process TLB Modified Exception
+/** Process TLB Modified Exception.
- *
- * Process TLB Modified Exception.
+ *
- * @param istate Interrupted register context.
+ * @param istate    Interrupted register context.
  */
 void tlb_modified(istate_t *istate)
+{
     tlb_index_t index;
     uintptr_t badvaddr;
      * Record access and write to PTE.
      */
     pte->a = 1;
     pte->d = 1;
-    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
+    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable,
+        pte->pfn);
     /*
      * The entry is to be updated in TLB.
      */
-    if ((badvaddr/PAGE_SIZE) % 2 == 0)
+    if ((badvaddr / PAGE_SIZE) % 2 == 0)
         cp0_entry_lo0_write(lo.value);
     else
         cp0_entry_lo1_write(lo.value);
     cp0_pagemask_write(TLB_PAGE_MASK_16K);
     tlbwi();
         symbol = s;
     s = get_symtab_entry(istate->ra);
     if (s)
         sym2 = s;
-    fault_if_from_uspace(istate, "TLB Refill Exception on %p", cp0_badvaddr_read());
+    fault_if_from_uspace(istate, "TLB Refill Exception on %p",
+        cp0_badvaddr_read());
-    panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);
+    panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(),
+        istate->epc, symbol, sym2);
+}
 void tlb_invalid_fail(istate_t *istate)
+{
     char *symbol = "";
     char *s = get_symtab_entry(istate->epc);
     if (s)
         symbol = s;
-    fault_if_from_uspace(istate, "TLB Invalid Exception on %p", cp0_badvaddr_read());
+    fault_if_from_uspace(istate, "TLB Invalid Exception on %p",
+        cp0_badvaddr_read());
-    panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
+    panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(),
+        istate->epc, symbol);
+}
 void tlb_modified_fail(istate_t *istate)
+{
     char *symbol = "";
     char *s = get_symtab_entry(istate->epc);
     if (s)
         symbol = s;
-    fault_if_from_uspace(istate, "TLB Modified Exception on %p", cp0_badvaddr_read());
+    fault_if_from_uspace(istate, "TLB Modified Exception on %p",
+        cp0_badvaddr_read());
-    panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
+    panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(),
+        istate->epc, symbol);
+}
-/** Try to find PTE for faulting address
+/** Try to find PTE for faulting address.
+ *
- * Try to find PTE for faulting address.
  * The AS->lock must be held on entry to this function.
+ *
- * @param badvaddr Faulting virtual address.
+ * @param badvaddr  Faulting virtual address.
- * @param access Access mode that caused the fault.
+ * @param access    Access mode that caused the fault.
- * @param istate Pointer to interrupted state.
+ * @param istate    Pointer to interrupted state.
- * @param pfrc Pointer to variable where as_page_fault() return code will be stored.
+ * @param pfrc      Pointer to variable where as_page_fault() return code
+ *          will be stored.
+ *
- * @return PTE on success, NULL otherwise.
+ * @return      PTE on success, NULL otherwise.
  */
+pte_t *
-pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc)
+find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate,
+    int *pfrc)
+{
     entry_hi_t hi;
     pte_t *pte;
     hi.value = cp0_entry_hi_read();
+        }
+    }
+}
+void
-void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)
+tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable,
+    uintptr_t pfn)
+{
     lo->value = 0;
     lo->g = g;
     lo->v = v;
     lo->d = d;
         hi.value = cp0_entry_hi_read();
         lo0.value = cp0_entry_lo0_read();
         lo1.value = cp0_entry_lo1_read();
         printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n",
             i, hi.asid, hi.vpn2, mask.mask,
             lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
         printf("                    %1u %1u %1u %1u %#6x\n",
             lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
+    }
     cp0_entry_hi_write(hi_save.value);
+}
     interrupts_restore(ipl);
     cp0_entry_hi_write(hi_save.value);
+}
-/** Invalidate TLB entries for specified page range belonging to specified address space.
+/** Invalidate TLB entries for specified page range belonging to specified
+ * address space.
+ *
- * @param asid Address space identifier.
+ * @param asid      Address space identifier.
- * @param page First page whose TLB entry is to be invalidated.
+ * @param page      First page whose TLB entry is to be invalidated.
- * @param cnt Number of entries to invalidate.
+ * @param cnt       Number of entries to invalidate.
  */
 void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
+{
     unsigned int i;
     ipl_t ipl;
         tlbp();
         index.value = cp0_index_read();
         if (!index.p) {
+            /*
-            /* Entry was found, index register contains valid index. */
+             * Entry was found, index register contains valid
+             * index.
+             */
             tlbr();
             lo0.value = cp0_entry_lo0_read();
             lo1.value = cp0_entry_lo1_read();

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/mips32/src/mm/tlb.c – Rev 3228 → 3392