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| 51 | #ifdef KERNEL |
51 | #ifdef KERNEL |
| 52 | 52 | ||
| 53 | /* |
53 | /* |
| 54 | * Implementation of generic 4-level page table interface. |
54 | * Implementation of generic 4-level page table interface. |
| 55 | * NOTE: this implementation is under construction |
- | |
| 56 | * |
55 | * |
| 57 | * Page table layout: |
56 | * Page table layout: |
| 58 | * - 32-bit virtual addresses |
57 | * - 32-bit virtual addresses |
| 59 | * - Offset is 14 bits => pages are 16K long |
58 | * - Offset is 14 bits => pages are 16K long |
| 60 | * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long |
59 | * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long |