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Line 46... | Line 46... | ||
46 | kernel_image_start: |
46 | kernel_image_start: |
47 | .auto |
47 | .auto |
48 | 48 | ||
49 | # Fill TR.i and TR.d using Region Register #VRN_KERNEL |
49 | # Fill TR.i and TR.d using Region Register #VRN_KERNEL |
50 | 50 | ||
51 | movl r8=(VRN_KERNEL<<VRN_SHIFT) |
51 | movl r8 = (VRN_KERNEL << VRN_SHIFT) |
52 | mov r9=rr[r8] |
52 | mov r9 = rr[r8] |
53 | movl r10=(RR_MASK) |
53 | movl r10 = (RR_MASK) |
54 | and r9=r10,r9 |
54 | and r9 = r10, r9 |
55 | movl r10=((RID_KERNEL<<RID_SHIFT)|(KERNEL_PAGE_WIDTH<<PS_SHIFT)) |
55 | movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT)) |
56 | or r9=r10,r9 |
56 | or r9 = r10, r9 |
57 | mov rr[r8]=r9 |
57 | mov rr[r8] = r9 |
58 | 58 | ||
59 | movl r8=(VRN_KERNEL<<VRN_SHIFT) |
59 | movl r8 = (VRN_KERNEL << VRN_SHIFT) |
60 | mov cr.ifa=r8 |
60 | mov cr.ifa = r8 |
61 | movl r10=(KERNEL_PAGE_WIDTH<<PS_SHIFT) |
61 | movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT) |
62 | mov cr.itir=r10 |
62 | mov cr.itir = r10 |
63 | movl r10=(KERNEL_TRANSLATION_I) |
63 | movl r10 = (KERNEL_TRANSLATION_I) |
64 | itr.i itr[r0]=r10 |
64 | itr.i itr[r0] = r10 |
65 | movl r10=(KERNEL_TRANSLATION_D) |
65 | movl r10 = (KERNEL_TRANSLATION_D) |
66 | itr.d dtr[r0]=r10 |
66 | itr.d dtr[r0] = r10 |
67 | 67 | ||
68 | # initialize PSR |
68 | # initialize PSR |
69 | mov psr.l = r0 |
69 | mov psr.l = r0 |
70 | srlz.i |
70 | srlz.i |
71 | srlz.d |
71 | srlz.d |
72 | movl r10=(PSR_DT_MASK|PSR_RT_MASK|PSR_IT_MASK|PSR_IC_MASK) /* Enable paging */ |
72 | movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */ |
73 | mov r9=psr |
73 | mov r9 = psr |
74 | or r10=r10,r9 |
74 | or r10 = r10, r9 |
75 | mov cr.ipsr=r10 |
75 | mov cr.ipsr = r10 |
76 | mov cr.ifs=r0 |
76 | mov cr.ifs = r0 |
77 | movl r8=paging_start |
77 | movl r8 = paging_start |
78 | mov cr.iip=r8 |
78 | mov cr.iip = r8 |
79 | srlz.d |
79 | srlz.d |
80 | srlz.i |
80 | srlz.i |
81 | 81 | ||
82 | .explicit |
82 | .explicit |
83 | /* |
83 | /* |
Line 95... | Line 95... | ||
95 | # switch to register bank 1 |
95 | # switch to register bank 1 |
96 | bsw.1 |
96 | bsw.1 |
97 | 97 | ||
98 | # initialize register stack |
98 | # initialize register stack |
99 | mov ar.rsc = r0 |
99 | mov ar.rsc = r0 |
100 | movl r8=(VRN_KERNEL<<VRN_SHIFT) ;; |
100 | movl r8 = (VRN_KERNEL << VRN_SHIFT) ;; |
101 | mov ar.bspstore = r8 |
101 | mov ar.bspstore = r8 |
102 | loadrs |
102 | loadrs |
103 | 103 | ||
104 | # initialize memory stack to some sane value |
104 | # initialize memory stack to some sane value |
105 | movl r12 = stack0;; |
105 | movl r12 = stack0 ;; |
106 | 106 | ||
107 | add r12 = - 16, r12 /* allocate a scratch area on the stack */ |
107 | add r12 = -16, r12 /* allocate a scratch area on the stack */ |
108 | 108 | ||
109 | # initialize gp (Global Pointer) register |
109 | # initialize gp (Global Pointer) register |
110 | movl r1 = _hardcoded_load_address |
110 | movl r1 = _hardcoded_load_address |
111 | 111 | ||
112 | /* |
112 | /* |
Line 121... | Line 121... | ||
121 | ;; |
121 | ;; |
122 | st8 [r17] = r14 |
122 | st8 [r17] = r14 |
123 | st8 [r18] = r15 |
123 | st8 [r18] = r15 |
124 | st8 [r19] = r16 |
124 | st8 [r19] = r16 |
125 | 125 | ||
126 | ssm (1<<19);; /* Disable f32 - f127 */ |
126 | ssm (1 << 19) ;; /* Disable f32 - f127 */ |
127 | srlz.i; |
127 | srlz.i |
128 | srlz.d;; |
128 | srlz.d ;; |
129 | 129 | ||
130 | br.call.sptk.many b0 = arch_pre_main |
130 | br.call.sptk.many b0 = arch_pre_main |
131 | 131 | ||
132 | movl r18=main_bsp ;; |
132 | movl r18 = main_bsp ;; |
133 | mov b1=r18 ;; |
133 | mov b1 = r18 ;; |
134 | br.call.sptk.many b0=b1 |
134 | br.call.sptk.many b0 = b1 |
135 | 135 | ||
136 | 136 | ||
137 | 0: |
137 | 0: |
138 | br 0b |
138 | br 0b |