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33 | 33 | ||
34 | #define RR_MASK (0xFFFFFFFF00000002) |
34 | #define RR_MASK (0xFFFFFFFF00000002) |
35 | #define RID_SHIFT 8 |
35 | #define RID_SHIFT 8 |
36 | #define PS_SHIFT 2 |
36 | #define PS_SHIFT 2 |
37 | 37 | ||
38 | #define KERNEL_TRANSLATION_I 0x0010000000000661 |
38 | #define KERNEL_TRANSLATION_I 0x0010000000000661 |
39 | #define KERNEL_TRANSLATION_D 0x0010000000000661 |
39 | #define KERNEL_TRANSLATION_D 0x0010000000000661 |
- | 40 | #define KERNEL_TRANSLATION_VIO 0x0010000000000671 |
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- | 41 | #define KERNEL_TRANSLATION_IO 0x00100FFFFC000671 |
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- | 42 | #define VIO_OFFSET 0x0002000000000000 |
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- | 43 | ||
- | 44 | #define IO_OFFSET 0x0001000000000000 |
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- | 45 | ||
- | 46 | ||
40 | 47 | ||
41 | .section K_TEXT_START, "ax" |
48 | .section K_TEXT_START, "ax" |
42 | 49 | ||
43 | .global kernel_image_start |
50 | .global kernel_image_start |
44 | 51 | ||
45 | stack0: |
52 | stack0: |
46 | kernel_image_start: |
53 | kernel_image_start: |
47 | .auto |
54 | .auto |
48 | 55 | ||
- | 56 | mov psr.l = r0 |
|
- | 57 | srlz.i |
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- | 58 | srlz.d |
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- | 59 | ||
49 | # Fill TR.i and TR.d using Region Register #VRN_KERNEL |
60 | # Fill TR.i and TR.d using Region Register #VRN_KERNEL |
50 | 61 | ||
- | 62 | ||
51 | movl r8 = (VRN_KERNEL << VRN_SHIFT) |
63 | movl r8 = (VRN_KERNEL << VRN_SHIFT) |
52 | mov r9 = rr[r8] |
64 | mov r9 = rr[r8] |
- | 65 | ||
- | 66 | ||
53 | movl r10 = (RR_MASK) |
67 | movl r10 = (RR_MASK) |
54 | and r9 = r10, r9 |
68 | and r9 = r10, r9 |
55 | movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT)) |
69 | movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT)) |
56 | or r9 = r10, r9 |
70 | or r9 = r10, r9 |
- | 71 | ||
- | 72 | ||
57 | mov rr[r8] = r9 |
73 | mov rr[r8] = r9 |
58 | 74 | ||
- | 75 | ||
- | 76 | ||
59 | movl r8 = (VRN_KERNEL << VRN_SHIFT) |
77 | movl r8 = (VRN_KERNEL << VRN_SHIFT) |
60 | mov cr.ifa = r8 |
78 | mov cr.ifa = r8 |
- | 79 | ||
- | 80 | ||
- | 81 | mov r11 = cr.itir ;; |
|
61 | movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT) |
82 | movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT);; |
- | 83 | or r10 =r10 , r11 ;; |
|
62 | mov cr.itir = r10 |
84 | mov cr.itir = r10;; |
- | 85 | ||
- | 86 | ||
63 | movl r10 = (KERNEL_TRANSLATION_I) |
87 | movl r10 = (KERNEL_TRANSLATION_I) |
64 | itr.i itr[r0] = r10 |
88 | itr.i itr[r0] = r10 |
- | 89 | ||
- | 90 | ||
65 | movl r10 = (KERNEL_TRANSLATION_D) |
91 | movl r10 = (KERNEL_TRANSLATION_D) |
66 | itr.d dtr[r0] = r10 |
92 | itr.d dtr[r0] = r10 |
67 | 93 | ||
- | 94 | ||
- | 95 | movl r7 = 1 |
|
- | 96 | movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET |
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- | 97 | mov cr.ifa = r8 |
|
- | 98 | movl r10 = (KERNEL_TRANSLATION_VIO) |
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- | 99 | itr.d dtr[r7] = r10 |
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- | 100 | ||
- | 101 | ||
- | 102 | mov r11 = cr.itir ;; |
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- | 103 | movl r10 = ~0xfc;; |
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- | 104 | and r10 =r10 , r11 ;; |
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- | 105 | movl r11 = (IO_PAGE_WIDTH << PS_SHIFT);; |
|
- | 106 | or r10 =r10 , r11 ;; |
|
- | 107 | mov cr.itir = r10;; |
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- | 108 | ||
- | 109 | ||
- | 110 | movl r7 = 2 |
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- | 111 | movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET |
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- | 112 | mov cr.ifa = r8 |
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- | 113 | movl r10 = (KERNEL_TRANSLATION_IO) |
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- | 114 | itr.d dtr[r7] = r10 |
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- | 115 | ||
- | 116 | ||
- | 117 | ||
- | 118 | ||
68 | # initialize PSR |
119 | # initialize PSR |
69 | mov psr.l = r0 |
- | |
70 | srlz.i |
- | |
71 | srlz.d |
- | |
72 | movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */ |
120 | movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */ |
73 | mov r9 = psr |
121 | mov r9 = psr |
74 | or r10 = r10, r9 |
122 | or r10 = r10, r9 |
75 | mov cr.ipsr = r10 |
123 | mov cr.ipsr = r10 |
76 | mov cr.ifs = r0 |
124 | mov cr.ifs = r0 |