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Line 70... | Line 70... | ||
70 | 70 | ||
71 | ipl = interrupts_disable(); |
71 | ipl = interrupts_disable(); |
72 | 72 | ||
73 | for(i = 0; i < count1; i++) { |
73 | for(i = 0; i < count1; i++) { |
74 | for(j = 0; j < count2; j++) { |
74 | for(j = 0; j < count2; j++) { |
75 | __asm__ volatile ( |
75 | asm volatile ( |
76 | "ptc.e %0 ;;" |
76 | "ptc.e %0 ;;" |
77 | : |
77 | : |
78 | : "r" (adr) |
78 | : "r" (adr) |
79 | ); |
79 | ); |
80 | adr += stride2; |
80 | adr += stride2; |
Line 177... | Line 177... | ||
177 | va&=~((1<<ps)-1); |
177 | va&=~((1<<ps)-1); |
178 | break; |
178 | break; |
179 | } |
179 | } |
180 | /*cnt+=(page!=va);*/ |
180 | /*cnt+=(page!=va);*/ |
181 | for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps)) { |
181 | for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps)) { |
182 | __asm__ volatile ( |
182 | asm volatile ( |
183 | "ptc.l %0,%1;;" |
183 | "ptc.l %0,%1;;" |
184 | : |
184 | : |
185 | : "r" (va), "r" (ps<<2) |
185 | : "r" (va), "r" (ps<<2) |
186 | ); |
186 | ); |
187 | } |
187 | } |
Line 242... | Line 242... | ||
242 | rr_write(VA2VRN(va), rr0.word); |
242 | rr_write(VA2VRN(va), rr0.word); |
243 | srlz_d(); |
243 | srlz_d(); |
244 | srlz_i(); |
244 | srlz_i(); |
245 | } |
245 | } |
246 | 246 | ||
247 | __asm__ volatile ( |
247 | asm volatile ( |
248 | "mov r8=psr;;\n" |
248 | "mov r8=psr;;\n" |
249 | "rsm %0;;\n" /* PSR_IC_MASK */ |
249 | "rsm %0;;\n" /* PSR_IC_MASK */ |
250 | "srlz.d;;\n" |
250 | "srlz.d;;\n" |
251 | "srlz.i;;\n" |
251 | "srlz.i;;\n" |
252 | "mov cr.ifa=%1\n" /* va */ |
252 | "mov cr.ifa=%1\n" /* va */ |
Line 318... | Line 318... | ||
318 | rr_write(VA2VRN(va), rr0.word); |
318 | rr_write(VA2VRN(va), rr0.word); |
319 | srlz_d(); |
319 | srlz_d(); |
320 | srlz_i(); |
320 | srlz_i(); |
321 | } |
321 | } |
322 | 322 | ||
323 | __asm__ volatile ( |
323 | asm volatile ( |
324 | "mov r8=psr;;\n" |
324 | "mov r8=psr;;\n" |
325 | "rsm %0;;\n" /* PSR_IC_MASK */ |
325 | "rsm %0;;\n" /* PSR_IC_MASK */ |
326 | "srlz.d;;\n" |
326 | "srlz.d;;\n" |
327 | "srlz.i;;\n" |
327 | "srlz.i;;\n" |
328 | "mov cr.ifa=%1\n" /* va */ |
328 | "mov cr.ifa=%1\n" /* va */ |
Line 380... | Line 380... | ||
380 | * @param page Virtual page address including VRN bits. |
380 | * @param page Virtual page address including VRN bits. |
381 | * @param width Width of the purge in bits. |
381 | * @param width Width of the purge in bits. |
382 | */ |
382 | */ |
383 | void dtr_purge(uintptr_t page, count_t width) |
383 | void dtr_purge(uintptr_t page, count_t width) |
384 | { |
384 | { |
385 | __asm__ volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2)); |
385 | asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2)); |
386 | } |
386 | } |
387 | 387 | ||
388 | 388 | ||
389 | /** Copy content of PTE into data translation cache. |
389 | /** Copy content of PTE into data translation cache. |
390 | * |
390 | * |