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| Rev 592 | Rev 595 | ||
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| 49 | 49 | ||
| 50 | # Improved support for hyperthreading |
50 | # Improved support for hyperthreading |
| 51 | ! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_HT (y/n) |
51 | ! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_HT (y/n) |
| 52 | 52 | ||
| 53 | # Lazy FPU context switching |
53 | # Lazy FPU context switching |
| 54 | ! [(ARCH=mips32&MIPS_MACHINE!=msim)|ARCH=amd64|ARCH=ia32] CONFIG_FPU_LAZY (y/n) |
54 | ! [(ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics)|ARCH=amd64|ARCH=ia32] CONFIG_FPU_LAZY (y/n) |
| 55 | 55 | ||
| 56 | ## Debugging configuration directives |
56 | ## Debugging configuration directives |
| 57 | 57 | ||
| 58 | # General debuging and assert checking |
58 | # General debuging and assert checking |
| 59 | ! CONFIG_DEBUG (y/n) |
59 | ! CONFIG_DEBUG (y/n) |
| Line 75... | Line 75... | ||
| 75 | @ "synch/rwlock5" Read write test 5 |
75 | @ "synch/rwlock5" Read write test 5 |
| 76 | @ "synch/semaphore1" Semaphore test 1 |
76 | @ "synch/semaphore1" Semaphore test 1 |
| 77 | @ "synch/semaphore2" Sempahore test 2 |
77 | @ "synch/semaphore2" Sempahore test 2 |
| 78 | @ [ARCH=ia32|ARCH=amd64] "fpu/fpu1" Intel fpu test 1 |
78 | @ [ARCH=ia32|ARCH=amd64] "fpu/fpu1" Intel fpu test 1 |
| 79 | @ [ARCH=ia32|ARCH=amd64] "fpu/sse1" Intel Sse test 1 |
79 | @ [ARCH=ia32|ARCH=amd64] "fpu/sse1" Intel Sse test 1 |
| 80 | @ [ARCH=mips32&MIPS_MACHINE!=msim] "fpu/mips1" Mips FPU test 1 |
80 | @ [ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics] "fpu/mips1" Mips FPU test 1 |
| 81 | @ "print/print1" Printf test 1 |
81 | @ "print/print1" Printf test 1 |
| 82 | @ "thread/thread1" Thread test 1 |
82 | @ "thread/thread1" Thread test 1 |
| 83 | @ "mm/mapping1" Mapping test 1 |
83 | @ "mm/mapping1" Mapping test 1 |
| 84 | ! CONFIG_TEST (choice) |
84 | ! CONFIG_TEST (choice) |