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1 | Memory management |
1 | Memory management |
2 | ================= |
2 | ================= |
3 | 3 | ||
- | 4 | 1. Virtual Address Translation |
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- | 5 | ||
- | 6 | 1.1 Hierarchical 4-level per address space page tables |
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- | 7 | ||
4 | SPARTAN kernel deploys generic interface for 4-level page tables, |
8 | SPARTAN kernel deploys generic interface for 4-level page tables |
- | 9 | for these architectures: amd64, ia32, mips32 and ppc32. In this |
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5 | no matter what the real underlying hardware architecture is. |
10 | setting, page tables are hierarchical and are not shared by |
- | 11 | address spaces (i.e. one set of page tables per address space). |
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6 | 12 | ||
7 | 13 | ||
8 | VADDR |
14 | VADDR |
9 | +-----------------------------------------------------------------------------+ |
15 | +-----------------------------------------------------------------------------+ |
10 | | PTL0_INDEX | PTL1_INDEX | PTL2_INDEX | PTL3_INDEX | OFFSET | |
16 | | PTL0_INDEX | PTL1_INDEX | PTL2_INDEX | PTL3_INDEX | OFFSET | |
Line 48... | Line 54... | ||
48 | 54 | ||
49 | 55 | ||
50 | On architectures whose hardware has fewer levels, PTL2 and, if need be, PTL1 are |
56 | On architectures whose hardware has fewer levels, PTL2 and, if need be, PTL1 are |
51 | left out. TLB-only architectures are to define custom format for software page |
57 | left out. TLB-only architectures are to define custom format for software page |
52 | tables. |
58 | tables. |
- | 59 | ||
- | 60 | ||
- | 61 | ||
- | 62 | 1.2 Single global page hash table |
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- | 63 | ||
- | 64 | Generic page hash table interface is deployed on 64-bit architectures without |
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- | 65 | implied hardware support for hierarchical page tables, i.e. ia64 and sparc64. |
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- | 66 | There is only one global page hash table in the system shared by all address |
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- | 67 | spaces. |