Rev 1735 | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 1735 | Rev 1780 | ||
|---|---|---|---|
| Line 129... | Line 129... | ||
| 129 | * @param frame Physical frame address. |
129 | * @param frame Physical frame address. |
| 130 | * @param pagesize Page size. |
130 | * @param pagesize Page size. |
| 131 | * @param locked True for permanent mappings, false otherwise. |
131 | * @param locked True for permanent mappings, false otherwise. |
| 132 | * @param cacheable True if the mapping is cacheable, false otherwise. |
132 | * @param cacheable True if the mapping is cacheable, false otherwise. |
| 133 | */ |
133 | */ |
| 134 | void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable) |
134 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable) |
| 135 | { |
135 | { |
| 136 | tlb_tag_access_reg_t tag; |
136 | tlb_tag_access_reg_t tag; |
| 137 | tlb_data_t data; |
137 | tlb_data_t data; |
| 138 | page_address_t pg; |
138 | page_address_t pg; |
| 139 | frame_address_t fr; |
139 | frame_address_t fr; |
| Line 168... | Line 168... | ||
| 168 | 168 | ||
| 169 | /** DTLB miss handler. */ |
169 | /** DTLB miss handler. */ |
| 170 | void fast_data_access_mmu_miss(void) |
170 | void fast_data_access_mmu_miss(void) |
| 171 | { |
171 | { |
| 172 | tlb_tag_access_reg_t tag; |
172 | tlb_tag_access_reg_t tag; |
| 173 | __address tpc; |
173 | uintptr_t tpc; |
| 174 | char *tpc_str; |
174 | char *tpc_str; |
| 175 | 175 | ||
| 176 | tag.value = dtlb_tag_access_read(); |
176 | tag.value = dtlb_tag_access_read(); |
| 177 | if (tag.context != ASID_KERNEL || tag.vpn == 0) { |
177 | if (tag.context != ASID_KERNEL || tag.vpn == 0) { |
| 178 | tpc = tpc_read(); |
178 | tpc = tpc_read(); |
| Line 266... | Line 266... | ||
| 266 | * |
266 | * |
| 267 | * @param asid Address Space ID. |
267 | * @param asid Address Space ID. |
| 268 | * @param page First page which to sweep out from ITLB and DTLB. |
268 | * @param page First page which to sweep out from ITLB and DTLB. |
| 269 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
269 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
| 270 | */ |
270 | */ |
| 271 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
271 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
| 272 | { |
272 | { |
| 273 | int i; |
273 | int i; |
| 274 | 274 | ||
| 275 | for (i = 0; i < cnt; i++) { |
275 | for (i = 0; i < cnt; i++) { |
| 276 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
276 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |