WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/sparc64/include/mm/tlb.h



 
/** Bit width of the TLB-locked portion of kernel address space. */
#define KERNEL_PAGE_WIDTH       22  /* 4M */
 
union tlb_context_reg {
    uint64_t v;
    struct {
        unsigned long : 51;
        unsigned context : 13;      /**< Context/ASID. */
    } __attribute__ ((packed));
};

/** I-/D-TLB Data In/Access Register type. */
typedef tte_data_t tlb_data_t;
 
/** I-/D-TLB Data Access Address in Alternate Space. */
union tlb_data_access_addr {
    uint64_t value;
    struct {
        uint64_t : 55;
        unsigned tlb_entry : 6;
        unsigned : 3;
    } __attribute__ ((packed));
};
typedef union tlb_data_access_addr tlb_data_access_addr_t;
typedef union tlb_data_access_addr tlb_tag_read_addr_t;
 
/** I-/D-TLB Tag Read Register. */
union tlb_tag_read_reg {
    uint64_t value;
    struct {
        uint64_t vpn : 51;      /**< Virtual Address bits 63:13. */
        unsigned context : 13;  /**< Context identifier. */
    } __attribute__ ((packed));
};
typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
typedef union tlb_tag_read_reg tlb_tag_access_reg_t;

#define TLB_DEMAP_SECONDARY 1
#define TLB_DEMAP_NUCLEUS   2
 
/** TLB Demap Operation Address. */
union tlb_demap_addr {
    uint64_t value;
    struct {
        uint64_t vpn: 51;       /**< Virtual Address bits 63:13. */
        unsigned : 6;       /**< Ignored. */
        unsigned type : 1;  /**< The type of demap operation. */
        unsigned context : 2;   /**< Context register selection. */
        unsigned : 4;       /**< Zero. */
    } __attribute__ ((packed));
};
typedef union tlb_demap_addr tlb_demap_addr_t;
 
/** TLB Synchronous Fault Status Register. */
union tlb_sfsr_reg {
    uint64_t value;
    struct {
        unsigned long : 39; /**< Implementation dependent. */
        unsigned nf : 1;    /**< Nonfaulting load. */
        unsigned asi : 8;   /**< ASI. */
        unsigned tm : 1;    /**< TLB miss. */

 
/** Read MMU Primary Context Register.
 *
 * @return Current value of Primary Context Register.
 */
static inline uint64_t mmu_primary_context_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
 *
 * @param v New value of Primary Context Register.
 */
static inline void mmu_primary_context_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
    flush();
}
 
/** Read MMU Secondary Context Register.
 *
 * @return Current value of Secondary Context Register.
 */
static inline uint64_t mmu_secondary_context_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
 *
 * @param v New value of Primary Context Register.
 */
static inline void mmu_secondary_context_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
    flush();
}
 

 *
 * @param entry TLB Entry index.
 *
 * @return Current value of specified IMMU TLB Data Access Register.
 */
static inline uint64_t itlb_data_access_read(index_t entry)
{
    tlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;

/** Write IMMU TLB Data Access Register.
 *
 * @param entry TLB Entry index.
 * @param value Value to be written.
 */
static inline void itlb_data_access_write(index_t entry, uint64_t value)
{
    tlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;

 *
 * @param entry TLB Entry index.
 *
 * @return Current value of specified DMMU TLB Data Access Register.
 */
static inline uint64_t dtlb_data_access_read(index_t entry)
{
    tlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;

/** Write DMMU TLB Data Access Register.
 *
 * @param entry TLB Entry index.
 * @param value Value to be written.
 */
static inline void dtlb_data_access_write(index_t entry, uint64_t value)
{
    tlb_data_access_addr_t reg;
   
    reg.value = 0;
    reg.tlb_entry = entry;

 *
 * @param entry TLB Entry index.
 *
 * @return Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(index_t entry)
{
    tlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_entry = entry;

 *
 * @param entry TLB Entry index.
 *
 * @return Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(index_t entry)
{
    tlb_tag_read_addr_t tag;
 
    tag.value = 0;
    tag.tlb_entry = entry;

 
/** Write IMMU TLB Tag Access Register.
 *
 * @param v Value to be written.
 */
static inline void itlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
    flush();
}
 
/** Read IMMU TLB Tag Access Register.
 *
 * @return Current value of IMMU TLB Tag Access Register.
 */
static inline uint64_t itlb_tag_access_read(void)
{
    return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
}
 
/** Write DMMU TLB Tag Access Register.
 *
 * @param v Value to be written.
 */
static inline void dtlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
    flush();
}
 
/** Read DMMU TLB Tag Access Register.
 *
 * @return Current value of DMMU TLB Tag Access Register.
 */
static inline uint64_t dtlb_tag_access_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
}
 
 
/** Write IMMU TLB Data in Register.
 *
 * @param v Value to be written.
 */
static inline void itlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
    flush();
}
 
/** Write DMMU TLB Data in Register.
 *
 * @param v Value to be written.
 */
static inline void dtlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
    flush();
}
 
/** Read ITLB Synchronous Fault Status Register.
 *
 * @return Current content of I-SFSR register.
 */
static inline uint64_t itlb_sfsr_read(void)
{
    return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
}
 
/** Write ITLB Synchronous Fault Status Register.
 *
 * @param v New value of I-SFSR register.
 */
static inline void itlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
    flush();
}
 
/** Read DTLB Synchronous Fault Status Register.
 *
 * @return Current content of D-SFSR register.
 */
static inline uint64_t dtlb_sfsr_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
}
 
/** Write DTLB Synchronous Fault Status Register.
 *
 * @param v New value of D-SFSR register.
 */
static inline void dtlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
    flush();
}
 
/** Read DTLB Synchronous Fault Address Register.
 *
 * @return Current content of D-SFAR register.
 */
static inline uint64_t dtlb_sfar_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
}
 
/** Perform IMMU TLB Demap Operation.
 *
 * @param type Selects between context and page demap.
 * @param context_encoding Specifies which Context register has Context ID for demap.
 * @param page Address which is on the page to be demapped.
 */
static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
{
    tlb_demap_addr_t da;
    page_address_t pg;
   
    da.value = 0;

 *
 * @param type Selects between context and page demap.
 * @param context_encoding Specifies which Context register has Context ID for demap.
 * @param page Address which is on the page to be demapped.
 */
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
{
    tlb_demap_addr_t da;
    page_address_t pg;
   
    da.value = 0;

 
extern void fast_instruction_access_mmu_miss(void);
extern void fast_data_access_mmu_miss(void);
extern void fast_data_access_protection(void);
 
extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
 
#endif
 
 /** @}
 */

Rev 1702	Rev 1780
Line 54...	Line 54...
54		54
55	/** Bit width of the TLB-locked portion of kernel address space. */	55	/** Bit width of the TLB-locked portion of kernel address space. */
56	#define KERNEL_PAGE_WIDTH 22 /* 4M */	56	#define KERNEL_PAGE_WIDTH 22 /* 4M */
57		57
58	union tlb_context_reg {	58	union tlb_context_reg {
59	__u64 v;	59	uint64_t v;
60	struct {	60	struct {
61	unsigned long : 51;	61	unsigned long : 51;
62	unsigned context : 13; /*< Context/ASID. /	62	unsigned context : 13; /*< Context/ASID. /
63	} __attribute__ ((packed));	63	} __attribute__ ((packed));
64	};	64	};
Line 67...	Line 67...
67	/** I-/D-TLB Data In/Access Register type. */	67	/** I-/D-TLB Data In/Access Register type. */
68	typedef tte_data_t tlb_data_t;	68	typedef tte_data_t tlb_data_t;
69		69
70	/** I-/D-TLB Data Access Address in Alternate Space. */	70	/** I-/D-TLB Data Access Address in Alternate Space. */
71	union tlb_data_access_addr {	71	union tlb_data_access_addr {
72	__u64 value;	72	uint64_t value;
73	struct {	73	struct {
74	__u64 : 55;	74	uint64_t : 55;
75	unsigned tlb_entry : 6;	75	unsigned tlb_entry : 6;
76	unsigned : 3;	76	unsigned : 3;
77	} __attribute__ ((packed));	77	} __attribute__ ((packed));
78	};	78	};
79	typedef union tlb_data_access_addr tlb_data_access_addr_t;	79	typedef union tlb_data_access_addr tlb_data_access_addr_t;
80	typedef union tlb_data_access_addr tlb_tag_read_addr_t;	80	typedef union tlb_data_access_addr tlb_tag_read_addr_t;
81		81
82	/** I-/D-TLB Tag Read Register. */	82	/** I-/D-TLB Tag Read Register. */
83	union tlb_tag_read_reg {	83	union tlb_tag_read_reg {
84	__u64 value;	84	uint64_t value;
85	struct {	85	struct {
86	__u64 vpn : 51; /*< Virtual Address bits 63:13. /	86	uint64_t vpn : 51; /*< Virtual Address bits 63:13. /
87	unsigned context : 13; /*< Context identifier. /	87	unsigned context : 13; /*< Context identifier. /
88	} __attribute__ ((packed));	88	} __attribute__ ((packed));
89	};	89	};
90	typedef union tlb_tag_read_reg tlb_tag_read_reg_t;	90	typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
91	typedef union tlb_tag_read_reg tlb_tag_access_reg_t;	91	typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
Line 99...	Line 99...
99	#define TLB_DEMAP_SECONDARY 1	99	#define TLB_DEMAP_SECONDARY 1
100	#define TLB_DEMAP_NUCLEUS 2	100	#define TLB_DEMAP_NUCLEUS 2
101		101
102	/** TLB Demap Operation Address. */	102	/** TLB Demap Operation Address. */
103	union tlb_demap_addr {	103	union tlb_demap_addr {
104	__u64 value;	104	uint64_t value;
105	struct {	105	struct {
106	__u64 vpn: 51; /*< Virtual Address bits 63:13. /	106	uint64_t vpn: 51; /*< Virtual Address bits 63:13. /
107	unsigned : 6; /*< Ignored. /	107	unsigned : 6; /*< Ignored. /
108	unsigned type : 1; /*< The type of demap operation. /	108	unsigned type : 1; /*< The type of demap operation. /
109	unsigned context : 2; /*< Context register selection. /	109	unsigned context : 2; /*< Context register selection. /
110	unsigned : 4; /*< Zero. /	110	unsigned : 4; /*< Zero. /
111	} __attribute__ ((packed));	111	} __attribute__ ((packed));
112	};	112	};
113	typedef union tlb_demap_addr tlb_demap_addr_t;	113	typedef union tlb_demap_addr tlb_demap_addr_t;
114		114
115	/** TLB Synchronous Fault Status Register. */	115	/** TLB Synchronous Fault Status Register. */
116	union tlb_sfsr_reg {	116	union tlb_sfsr_reg {
117	__u64 value;	117	uint64_t value;
118	struct {	118	struct {
119	unsigned long : 39; /*< Implementation dependent. /	119	unsigned long : 39; /*< Implementation dependent. /
120	unsigned nf : 1; /*< Nonfaulting load. /	120	unsigned nf : 1; /*< Nonfaulting load. /
121	unsigned asi : 8; /*< ASI. /	121	unsigned asi : 8; /*< ASI. /
122	unsigned tm : 1; /*< TLB miss. /	122	unsigned tm : 1; /*< TLB miss. /
Line 134...	Line 134...
134		134
135	/** Read MMU Primary Context Register.	135	/** Read MMU Primary Context Register.
136	*	136	*
137	* @return Current value of Primary Context Register.	137	* @return Current value of Primary Context Register.
138	*/	138	*/
139	static inline __u64 mmu_primary_context_read(void)	139	static inline uint64_t mmu_primary_context_read(void)
140	{	140	{
141	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);	141	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
142	}	142	}
143		143
144	/** Write MMU Primary Context Register.	144	/** Write MMU Primary Context Register.
145	*	145	*
146	* @param v New value of Primary Context Register.	146	* @param v New value of Primary Context Register.
147	*/	147	*/
148	static inline void mmu_primary_context_write(__u64 v)	148	static inline void mmu_primary_context_write(uint64_t v)
149	{	149	{
150	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);	150	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
151	flush();	151	flush();
152	}	152	}
153		153
154	/** Read MMU Secondary Context Register.	154	/** Read MMU Secondary Context Register.
155	*	155	*
156	* @return Current value of Secondary Context Register.	156	* @return Current value of Secondary Context Register.
157	*/	157	*/
158	static inline __u64 mmu_secondary_context_read(void)	158	static inline uint64_t mmu_secondary_context_read(void)
159	{	159	{
160	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);	160	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
161	}	161	}
162		162
163	/** Write MMU Primary Context Register.	163	/** Write MMU Primary Context Register.
164	*	164	*
165	* @param v New value of Primary Context Register.	165	* @param v New value of Primary Context Register.
166	*/	166	*/
167	static inline void mmu_secondary_context_write(__u64 v)	167	static inline void mmu_secondary_context_write(uint64_t v)
168	{	168	{
169	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);	169	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
170	flush();	170	flush();
171	}	171	}
172		172
Line 174...	Line 174...
174	*	174	*
175	* @param entry TLB Entry index.	175	* @param entry TLB Entry index.
176	*	176	*
177	* @return Current value of specified IMMU TLB Data Access Register.	177	* @return Current value of specified IMMU TLB Data Access Register.
178	*/	178	*/
179	static inline __u64 itlb_data_access_read(index_t entry)	179	static inline uint64_t itlb_data_access_read(index_t entry)
180	{	180	{
181	tlb_data_access_addr_t reg;	181	tlb_data_access_addr_t reg;
182		182
183	reg.value = 0;	183	reg.value = 0;
184	reg.tlb_entry = entry;	184	reg.tlb_entry = entry;
Line 188...	Line 188...
188	/** Write IMMU TLB Data Access Register.	188	/** Write IMMU TLB Data Access Register.
189	*	189	*
190	* @param entry TLB Entry index.	190	* @param entry TLB Entry index.
191	* @param value Value to be written.	191	* @param value Value to be written.
192	*/	192	*/
193	static inline void itlb_data_access_write(index_t entry, __u64 value)	193	static inline void itlb_data_access_write(index_t entry, uint64_t value)
194	{	194	{
195	tlb_data_access_addr_t reg;	195	tlb_data_access_addr_t reg;
196		196
197	reg.value = 0;	197	reg.value = 0;
198	reg.tlb_entry = entry;	198	reg.tlb_entry = entry;
Line 204...	Line 204...
204	*	204	*
205	* @param entry TLB Entry index.	205	* @param entry TLB Entry index.
206	*	206	*
207	* @return Current value of specified DMMU TLB Data Access Register.	207	* @return Current value of specified DMMU TLB Data Access Register.
208	*/	208	*/
209	static inline __u64 dtlb_data_access_read(index_t entry)	209	static inline uint64_t dtlb_data_access_read(index_t entry)
210	{	210	{
211	tlb_data_access_addr_t reg;	211	tlb_data_access_addr_t reg;
212		212
213	reg.value = 0;	213	reg.value = 0;
214	reg.tlb_entry = entry;	214	reg.tlb_entry = entry;
Line 218...	Line 218...
218	/** Write DMMU TLB Data Access Register.	218	/** Write DMMU TLB Data Access Register.
219	*	219	*
220	* @param entry TLB Entry index.	220	* @param entry TLB Entry index.
221	* @param value Value to be written.	221	* @param value Value to be written.
222	*/	222	*/
223	static inline void dtlb_data_access_write(index_t entry, __u64 value)	223	static inline void dtlb_data_access_write(index_t entry, uint64_t value)
224	{	224	{
225	tlb_data_access_addr_t reg;	225	tlb_data_access_addr_t reg;
226		226
227	reg.value = 0;	227	reg.value = 0;
228	reg.tlb_entry = entry;	228	reg.tlb_entry = entry;
Line 234...	Line 234...
234	*	234	*
235	* @param entry TLB Entry index.	235	* @param entry TLB Entry index.
236	*	236	*
237	* @return Current value of specified IMMU TLB Tag Read Register.	237	* @return Current value of specified IMMU TLB Tag Read Register.
238	*/	238	*/
239	static inline __u64 itlb_tag_read_read(index_t entry)	239	static inline uint64_t itlb_tag_read_read(index_t entry)
240	{	240	{
241	tlb_tag_read_addr_t tag;	241	tlb_tag_read_addr_t tag;
242		242
243	tag.value = 0;	243	tag.value = 0;
244	tag.tlb_entry = entry;	244	tag.tlb_entry = entry;
Line 249...	Line 249...
249	*	249	*
250	* @param entry TLB Entry index.	250	* @param entry TLB Entry index.
251	*	251	*
252	* @return Current value of specified DMMU TLB Tag Read Register.	252	* @return Current value of specified DMMU TLB Tag Read Register.
253	*/	253	*/
254	static inline __u64 dtlb_tag_read_read(index_t entry)	254	static inline uint64_t dtlb_tag_read_read(index_t entry)
255	{	255	{
256	tlb_tag_read_addr_t tag;	256	tlb_tag_read_addr_t tag;
257		257
258	tag.value = 0;	258	tag.value = 0;
259	tag.tlb_entry = entry;	259	tag.tlb_entry = entry;
Line 262...	Line 262...
262		262
263	/** Write IMMU TLB Tag Access Register.	263	/** Write IMMU TLB Tag Access Register.
264	*	264	*
265	* @param v Value to be written.	265	* @param v Value to be written.
266	*/	266	*/
267	static inline void itlb_tag_access_write(__u64 v)	267	static inline void itlb_tag_access_write(uint64_t v)
268	{	268	{
269	asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);	269	asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
270	flush();	270	flush();
271	}	271	}
272		272
273	/** Read IMMU TLB Tag Access Register.	273	/** Read IMMU TLB Tag Access Register.
274	*	274	*
275	* @return Current value of IMMU TLB Tag Access Register.	275	* @return Current value of IMMU TLB Tag Access Register.
276	*/	276	*/
277	static inline __u64 itlb_tag_access_read(void)	277	static inline uint64_t itlb_tag_access_read(void)
278	{	278	{
279	return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);	279	return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
280	}	280	}
281		281
282	/** Write DMMU TLB Tag Access Register.	282	/** Write DMMU TLB Tag Access Register.
283	*	283	*
284	* @param v Value to be written.	284	* @param v Value to be written.
285	*/	285	*/
286	static inline void dtlb_tag_access_write(__u64 v)	286	static inline void dtlb_tag_access_write(uint64_t v)
287	{	287	{
288	asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);	288	asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
289	flush();	289	flush();
290	}	290	}
291		291
292	/** Read DMMU TLB Tag Access Register.	292	/** Read DMMU TLB Tag Access Register.
293	*	293	*
294	* @return Current value of DMMU TLB Tag Access Register.	294	* @return Current value of DMMU TLB Tag Access Register.
295	*/	295	*/
296	static inline __u64 dtlb_tag_access_read(void)	296	static inline uint64_t dtlb_tag_access_read(void)
297	{	297	{
298	return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);	298	return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
299	}	299	}
300		300
301		301
302	/** Write IMMU TLB Data in Register.	302	/** Write IMMU TLB Data in Register.
303	*	303	*
304	* @param v Value to be written.	304	* @param v Value to be written.
305	*/	305	*/
306	static inline void itlb_data_in_write(__u64 v)	306	static inline void itlb_data_in_write(uint64_t v)
307	{	307	{
308	asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);	308	asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
309	flush();	309	flush();
310	}	310	}
311		311
312	/** Write DMMU TLB Data in Register.	312	/** Write DMMU TLB Data in Register.
313	*	313	*
314	* @param v Value to be written.	314	* @param v Value to be written.
315	*/	315	*/
316	static inline void dtlb_data_in_write(__u64 v)	316	static inline void dtlb_data_in_write(uint64_t v)
317	{	317	{
318	asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);	318	asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
319	flush();	319	flush();
320	}	320	}
321		321
322	/** Read ITLB Synchronous Fault Status Register.	322	/** Read ITLB Synchronous Fault Status Register.
323	*	323	*
324	* @return Current content of I-SFSR register.	324	* @return Current content of I-SFSR register.
325	*/	325	*/
326	static inline __u64 itlb_sfsr_read(void)	326	static inline uint64_t itlb_sfsr_read(void)
327	{	327	{
328	return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);	328	return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
329	}	329	}
330		330
331	/** Write ITLB Synchronous Fault Status Register.	331	/** Write ITLB Synchronous Fault Status Register.
332	*	332	*
333	* @param v New value of I-SFSR register.	333	* @param v New value of I-SFSR register.
334	*/	334	*/
335	static inline void itlb_sfsr_write(__u64 v)	335	static inline void itlb_sfsr_write(uint64_t v)
336	{	336	{
337	asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);	337	asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
338	flush();	338	flush();
339	}	339	}
340		340
341	/** Read DTLB Synchronous Fault Status Register.	341	/** Read DTLB Synchronous Fault Status Register.
342	*	342	*
343	* @return Current content of D-SFSR register.	343	* @return Current content of D-SFSR register.
344	*/	344	*/
345	static inline __u64 dtlb_sfsr_read(void)	345	static inline uint64_t dtlb_sfsr_read(void)
346	{	346	{
347	return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);	347	return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
348	}	348	}
349		349
350	/** Write DTLB Synchronous Fault Status Register.	350	/** Write DTLB Synchronous Fault Status Register.
351	*	351	*
352	* @param v New value of D-SFSR register.	352	* @param v New value of D-SFSR register.
353	*/	353	*/
354	static inline void dtlb_sfsr_write(__u64 v)	354	static inline void dtlb_sfsr_write(uint64_t v)
355	{	355	{
356	asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);	356	asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
357	flush();	357	flush();
358	}	358	}
359		359
360	/** Read DTLB Synchronous Fault Address Register.	360	/** Read DTLB Synchronous Fault Address Register.
361	*	361	*
362	* @return Current content of D-SFAR register.	362	* @return Current content of D-SFAR register.
363	*/	363	*/
364	static inline __u64 dtlb_sfar_read(void)	364	static inline uint64_t dtlb_sfar_read(void)
365	{	365	{
366	return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);	366	return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
367	}	367	}
368		368
369	/** Perform IMMU TLB Demap Operation.	369	/** Perform IMMU TLB Demap Operation.
370	*	370	*
371	* @param type Selects between context and page demap.	371	* @param type Selects between context and page demap.
372	* @param context_encoding Specifies which Context register has Context ID for demap.	372	* @param context_encoding Specifies which Context register has Context ID for demap.
373	* @param page Address which is on the page to be demapped.	373	* @param page Address which is on the page to be demapped.
374	*/	374	*/
375	static inline void itlb_demap(int type, int context_encoding, __address page)	375	static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
376	{	376	{
377	tlb_demap_addr_t da;	377	tlb_demap_addr_t da;
378	page_address_t pg;	378	page_address_t pg;
379		379
380	da.value = 0;	380	da.value = 0;
Line 392...	Line 392...
392	*	392	*
393	* @param type Selects between context and page demap.	393	* @param type Selects between context and page demap.
394	* @param context_encoding Specifies which Context register has Context ID for demap.	394	* @param context_encoding Specifies which Context register has Context ID for demap.
395	* @param page Address which is on the page to be demapped.	395	* @param page Address which is on the page to be demapped.
396	*/	396	*/
397	static inline void dtlb_demap(int type, int context_encoding, __address page)	397	static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
398	{	398	{
399	tlb_demap_addr_t da;	399	tlb_demap_addr_t da;
400	page_address_t pg;	400	page_address_t pg;
401		401
402	da.value = 0;	402	da.value = 0;
Line 412...	Line 412...
412		412
413	extern void fast_instruction_access_mmu_miss(void);	413	extern void fast_instruction_access_mmu_miss(void);
414	extern void fast_data_access_mmu_miss(void);	414	extern void fast_data_access_mmu_miss(void);
415	extern void fast_data_access_protection(void);	415	extern void fast_data_access_protection(void);
416		416
417	extern void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable);	417	extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
418		418
419	#endif	419	#endif
420		420
421	/** @}	421	/** @}
422	*/	422	*/

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(root)/kernel/trunk/arch/sparc64/include/mm/tlb.h – Rev 1702 → 1780