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| 37 | 37 | ||
| 38 | #define memory_barrier() |
38 | #define memory_barrier() |
| 39 | #define read_barrier() |
39 | #define read_barrier() |
| 40 | #define write_barrier() |
40 | #define write_barrier() |
| 41 | 41 | ||
| 42 | /** Flush Instruction Memory. */ |
42 | /** Flush Instruction Memory instruction. */ |
| 43 | static inline void flush(void) |
43 | static inline void flush(void) |
| 44 | { |
44 | { |
| 45 | /* |
45 | /* |
| 46 | * The FLUSH instruction takes address parameter, |
46 | * The FLUSH instruction takes address parameter. |
| 47 | * but JPS1 implementations are free to ignore it. |
47 | * As such, it may trap if the address is not found in DTLB. |
| 48 | * The only requirement is that it is a valid address |
48 | * However, JPS1 implementations are free to ignore the trap. |
| 49 | * as it is passed to D-MMU. |
- | |
| 50 | */ |
49 | */ |
| 51 | __asm__ volatile ("flush %sp\n"); /* %sp is guaranteed to reference mapped memory */ |
50 | __asm__ volatile ("flush %sp\n"); |
| 52 | } |
51 | } |
| 53 | 52 | ||
| - | 53 | /** Memory Barrier instruction. */ |
|
| 54 | static inline void membar(void) |
54 | static inline void membar(void) |
| 55 | { |
55 | { |
| 56 | __asm__ volatile ("membar #Sync\n"); |
56 | __asm__ volatile ("membar #Sync\n"); |
| 57 | } |
57 | } |
| 58 | 58 | ||