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static inline void pstate_write(__u64 v)
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static inline void pstate_write(__u64 v)
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{
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{
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    __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
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    __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
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}
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}
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/** Read TICK_compare Register.
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 *
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 * @return Value of TICK_comapre register.
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 */
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static inline __u64 tick_compare_read(void)
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{
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    __u64 v;
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    __asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
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    return v;
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}
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/** Write TICK_compare Register.
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 *
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 * @param New value of TICK_comapre register.
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 */
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static inline void tick_compare_write(__u64 v)
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{
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    __asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
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}
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/** Read TICK Register.
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 *
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 * @return Value of TICK register.
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 */
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static inline __u64 tick_read(void)
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{
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    __u64 v;
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    __asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
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    return v;
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}
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/** Write TICK Register.
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 *
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 * @param New value of TICK register.
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 */
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static inline void tick_write(__u64 v)
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{
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    __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
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}
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/** Enable interrupts.
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/** Enable interrupts.
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 *
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 *
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 * Enable interrupts and return previous
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 * Enable interrupts and return previous
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 * value of IPL.
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 * value of IPL.
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static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
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static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
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{
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{
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    __asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" (asi) : "memory");
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    __asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" (asi) : "memory");
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}
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}
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void cpu_halt(void);
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void cpu_halt(void);
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void cpu_sleep(void);
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void cpu_sleep(void);
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void asm_delay_loop(__u32 t);
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void asm_delay_loop(__u32 t);
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#endif
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#endif