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| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | #ifndef __sparc64_ASM_H__ |
29 | #ifndef __sparc64_ASM_H__ |
| 30 | #define __sparc64_ASM_H__ |
30 | #define __sparc64_ASM_H__ |
| 31 | 31 | ||
| - | 32 | #include <typedefs.h> |
|
| 32 | #include <arch/types.h> |
33 | #include <arch/types.h> |
| - | 34 | #include <arch/register.h> |
|
| 33 | #include <config.h> |
35 | #include <config.h> |
| 34 | 36 | ||
| - | 37 | /** Read Processor State register. |
|
| - | 38 | * |
|
| - | 39 | * @return Value of PSTATE register. |
|
| - | 40 | */ |
|
| - | 41 | static inline __u64 pstate_read(void) |
|
| - | 42 | { |
|
| - | 43 | __u64 v; |
|
| - | 44 | ||
| - | 45 | __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v)); |
|
| - | 46 | ||
| - | 47 | return v; |
|
| - | 48 | } |
|
| - | 49 | ||
| - | 50 | /** Write Processor State register. |
|
| - | 51 | * |
|
| - | 52 | * @param New value of PSTATE register. |
|
| - | 53 | */ |
|
| - | 54 | static inline void pstate_write(__u64 v) |
|
| - | 55 | { |
|
| - | 56 | __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
|
| - | 57 | } |
|
| - | 58 | ||
| - | 59 | ||
| 35 | /** Enable interrupts. |
60 | /** Enable interrupts. |
| 36 | * |
61 | * |
| 37 | * Enable interrupts and return previous |
62 | * Enable interrupts and return previous |
| 38 | * value of IPL. |
63 | * value of IPL. |
| 39 | * |
64 | * |
| 40 | * @return Old interrupt priority level. |
65 | * @return Old interrupt priority level. |
| 41 | */ |
66 | */ |
| 42 | static inline ipl_t interrupts_enable(void) { |
67 | static inline ipl_t interrupts_enable(void) { |
| - | 68 | pstate_reg_t pstate; |
|
| - | 69 | __u64 value; |
|
| - | 70 | ||
| - | 71 | value = pstate_read(); |
|
| - | 72 | pstate.value = value; |
|
| - | 73 | pstate.ie = true; |
|
| - | 74 | pstate_write(pstate.value); |
|
| - | 75 | ||
| - | 76 | return (ipl_t) value; |
|
| 43 | } |
77 | } |
| 44 | 78 | ||
| 45 | /** Disable interrupts. |
79 | /** Disable interrupts. |
| 46 | * |
80 | * |
| 47 | * Disable interrupts and return previous |
81 | * Disable interrupts and return previous |
| 48 | * value of IPL. |
82 | * value of IPL. |
| 49 | * |
83 | * |
| 50 | * @return Old interrupt priority level. |
84 | * @return Old interrupt priority level. |
| 51 | */ |
85 | */ |
| 52 | static inline ipl_t interrupts_disable(void) { |
86 | static inline ipl_t interrupts_disable(void) { |
| - | 87 | pstate_reg_t pstate; |
|
| - | 88 | __u64 value; |
|
| - | 89 | ||
| - | 90 | value = pstate_read(); |
|
| - | 91 | pstate.value = value; |
|
| - | 92 | pstate.ie = false; |
|
| - | 93 | pstate_write(pstate.value); |
|
| - | 94 | ||
| - | 95 | return (ipl_t) value; |
|
| 53 | } |
96 | } |
| 54 | 97 | ||
| 55 | /** Restore interrupt priority level. |
98 | /** Restore interrupt priority level. |
| 56 | * |
99 | * |
| 57 | * Restore IPL. |
100 | * Restore IPL. |
| 58 | * |
101 | * |
| 59 | * @param ipl Saved interrupt priority level. |
102 | * @param ipl Saved interrupt priority level. |
| 60 | */ |
103 | */ |
| 61 | static inline void interrupts_restore(ipl_t ipl) { |
104 | static inline void interrupts_restore(ipl_t ipl) { |
| - | 105 | pstate_reg_t pstate; |
|
| - | 106 | ||
| - | 107 | pstate.value = pstate_read(); |
|
| - | 108 | pstate.ie = ((pstate_reg_t) ipl).ie; |
|
| - | 109 | pstate_write(pstate.value); |
|
| 62 | } |
110 | } |
| 63 | 111 | ||
| 64 | /** Return interrupt priority level. |
112 | /** Return interrupt priority level. |
| 65 | * |
113 | * |
| 66 | * Return IPL. |
114 | * Return IPL. |
| 67 | * |
115 | * |
| 68 | * @return Current interrupt priority level. |
116 | * @return Current interrupt priority level. |
| 69 | */ |
117 | */ |
| 70 | static inline ipl_t interrupts_read(void) { |
118 | static inline ipl_t interrupts_read(void) { |
| - | 119 | return (ipl_t) pstate_read(); |
|
| 71 | } |
120 | } |
| 72 | 121 | ||
| 73 | /** Return base address of current stack. |
122 | /** Return base address of current stack. |
| 74 | * |
123 | * |
| 75 | * Return the base address of the current stack. |
124 | * Return the base address of the current stack. |
| Line 78... | Line 127... | ||
| 78 | */ |
127 | */ |
| 79 | static inline __address get_stack_base(void) |
128 | static inline __address get_stack_base(void) |
| 80 | { |
129 | { |
| 81 | __address v; |
130 | __address v; |
| 82 | 131 | ||
| 83 | __asm__ volatile ("and %%o6, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
132 | __asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
| 84 | 133 | ||
| 85 | return v; |
134 | return v; |
| 86 | } |
135 | } |
| 87 | 136 | ||
| 88 | /** Read Version Register. |
137 | /** Read Version Register. |