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| Rev 1702 | Rev 1708 | ||
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| Line 53... | Line 53... | ||
| 53 | return v; |
53 | return v; |
| 54 | } |
54 | } |
| 55 | 55 | ||
| 56 | /** Write Processor State register. |
56 | /** Write Processor State register. |
| 57 | * |
57 | * |
| 58 | * @param New value of PSTATE register. |
58 | * @param v New value of PSTATE register. |
| 59 | */ |
59 | */ |
| 60 | static inline void pstate_write(__u64 v) |
60 | static inline void pstate_write(__u64 v) |
| 61 | { |
61 | { |
| 62 | __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
62 | __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
| 63 | } |
63 | } |
| Line 75... | Line 75... | ||
| 75 | return v; |
75 | return v; |
| 76 | } |
76 | } |
| 77 | 77 | ||
| 78 | /** Write TICK_compare Register. |
78 | /** Write TICK_compare Register. |
| 79 | * |
79 | * |
| 80 | * @param New value of TICK_comapre register. |
80 | * @param v New value of TICK_comapre register. |
| 81 | */ |
81 | */ |
| 82 | static inline void tick_compare_write(__u64 v) |
82 | static inline void tick_compare_write(__u64 v) |
| 83 | { |
83 | { |
| 84 | __asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
84 | __asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
| 85 | } |
85 | } |
| Line 97... | Line 97... | ||
| 97 | return v; |
97 | return v; |
| 98 | } |
98 | } |
| 99 | 99 | ||
| 100 | /** Write TICK Register. |
100 | /** Write TICK Register. |
| 101 | * |
101 | * |
| 102 | * @param New value of TICK register. |
102 | * @param v New value of TICK register. |
| 103 | */ |
103 | */ |
| 104 | static inline void tick_write(__u64 v) |
104 | static inline void tick_write(__u64 v) |
| 105 | { |
105 | { |
| 106 | __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
106 | __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
| 107 | } |
107 | } |
| Line 119... | Line 119... | ||
| 119 | return v; |
119 | return v; |
| 120 | } |
120 | } |
| 121 | 121 | ||
| 122 | /** Write SOFTINT Register. |
122 | /** Write SOFTINT Register. |
| 123 | * |
123 | * |
| 124 | * @param New value of SOFTINT register. |
124 | * @param v New value of SOFTINT register. |
| 125 | */ |
125 | */ |
| 126 | static inline void softint_write(__u64 v) |
126 | static inline void softint_write(__u64 v) |
| 127 | { |
127 | { |
| 128 | __asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0)); |
128 | __asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0)); |
| 129 | } |
129 | } |
| 130 | 130 | ||
| 131 | /** Write CLEAR_SOFTINT Register. |
131 | /** Write CLEAR_SOFTINT Register. |
| 132 | * |
132 | * |
| 133 | * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. |
133 | * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. |
| 134 | * |
134 | * |
| 135 | * @param New value of CLEAR_SOFTINT register. |
135 | * @param v New value of CLEAR_SOFTINT register. |
| 136 | */ |
136 | */ |
| 137 | static inline void clear_softint_write(__u64 v) |
137 | static inline void clear_softint_write(__u64 v) |
| 138 | { |
138 | { |
| 139 | __asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
139 | __asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
| 140 | } |
140 | } |
| Line 268... | Line 268... | ||
| 268 | return v; |
268 | return v; |
| 269 | } |
269 | } |
| 270 | 270 | ||
| 271 | /** Write Trap Base Address register. |
271 | /** Write Trap Base Address register. |
| 272 | * |
272 | * |
| 273 | * @param New value of TBA. |
273 | * @param v New value of TBA. |
| 274 | */ |
274 | */ |
| 275 | static inline void tba_write(__u64 v) |
275 | static inline void tba_write(__u64 v) |
| 276 | { |
276 | { |
| 277 | __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); |
277 | __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); |
| 278 | } |
278 | } |