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Line 362... | Line 362... | ||
362 | } |
362 | } |
363 | 363 | ||
364 | 364 | ||
365 | void tlb_invalidate_asid(asid_t asid) |
365 | void tlb_invalidate_asid(asid_t asid) |
366 | { |
366 | { |
- | 367 | __u32 sdr1; |
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- | 368 | asm volatile ( |
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- | 369 | "mfsdr1 %0\n" |
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- | 370 | : "=r" (sdr1) |
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- | 371 | ); |
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- | 372 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
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- | 373 | ||
367 | // TODO |
374 | __u32 i; |
- | 375 | for (i = 0; i < 8192; i++) { |
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- | 376 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && (phte[i].vsid < ((asid << 4) + 16))) |
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- | 377 | phte[i].v = 0; |
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- | 378 | } |
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368 | tlb_invalidate_all(); |
379 | tlb_invalidate_all(); |
369 | } |
380 | } |
370 | 381 | ||
371 | 382 | ||
372 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
383 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |