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| Rev 1730 | Rev 1733 | ||
|---|---|---|---|
| Line 53... | Line 53... | ||
| 53 | */ |
53 | */ |
| 54 | void as_install_arch(as_t *as) |
54 | void as_install_arch(as_t *as) |
| 55 | { |
55 | { |
| 56 | asid_t asid; |
56 | asid_t asid; |
| 57 | ipl_t ipl; |
57 | ipl_t ipl; |
| 58 | __u8 sr; |
58 | __u32 sr; |
| 59 | 59 | ||
| 60 | ipl = interrupts_disable(); |
60 | ipl = interrupts_disable(); |
| 61 | spinlock_lock(&as->lock); |
61 | spinlock_lock(&as->lock); |
| 62 | 62 | ||
| 63 | asid = as->asid; |
63 | asid = as->asid; |
| Line 65... | Line 65... | ||
| 65 | /* Lower 2 GB, user and supervisor access */ |
65 | /* Lower 2 GB, user and supervisor access */ |
| 66 | for (sr = 0; sr < 8; sr++) { |
66 | for (sr = 0; sr < 8; sr++) { |
| 67 | asm volatile ( |
67 | asm volatile ( |
| 68 | "mtsrin %0, %1\n" |
68 | "mtsrin %0, %1\n" |
| 69 | : |
69 | : |
| 70 | : "r" (0x6000 + (asid << 4) + sr), "r" (sr * 0x1000) |
70 | : "r" ((0x6000 << 16) + (asid << 4) + sr), "r" (sr << 28) |
| 71 | ); |
71 | ); |
| 72 | } |
72 | } |
| 73 | 73 | ||
| 74 | /* Upper 2 GB, only supervisor access */ |
74 | /* Upper 2 GB, only supervisor access */ |
| 75 | for (sr = 8; sr < 16; sr++) { |
75 | for (sr = 8; sr < 16; sr++) { |
| 76 | asm volatile ( |
76 | asm volatile ( |
| 77 | "mtsrin %0, %1\n" |
77 | "mtsrin %0, %1\n" |
| 78 | : |
78 | : |
| 79 | : "r" (0x4000 + (asid << 4) + sr), "r" (sr * 0x1000) |
79 | : "r" ((0x4000 << 16) + (asid << 4) + sr), "r" (sr << 28) |
| 80 | ); |
80 | ); |
| 81 | } |
81 | } |
| 82 | 82 | ||
| 83 | spinlock_unlock(&as->lock); |
83 | spinlock_unlock(&as->lock); |
| 84 | interrupts_restore(ipl); |
84 | interrupts_restore(ipl); |