Subversion Repositories HelenOS-historic

Rev

Rev 534 | Rev 1004 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 534 Rev 845
Line 24... Line 24...
24 
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 24 
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 25 
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 26 
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 
 */
 27 
 */
28 
 
 28 
 
29 
#ifndef __ppc32_MACRO_H__
 29 
#ifndef __ppc32_REGNAME_H__
30 
#define __ppc32_MACRO_H__
 30 
#define __ppc32_REGNAME_H__
31 
 
 31 
 
32 
/*
 - 
 
33 
 * PPC assembler macros
 - 
 
34 
 */
 - 
 
35 
 
 - 
 
36 
/* Condition Register Bit Fields */
 32 
/* Condition Register Bit Fields */
37 
#define cr0 0
 33 
#define cr0 0
38 
#define cr1 1
 34 
#define cr1 1
39 
#define cr2 2
 35 
#define cr2 2
40 
#define cr3 3
 36 
#define cr3 3
Line 79... Line 75...
79 
 
 75 
 
80 
/* GPR Aliases */
 76 
/* GPR Aliases */
81 
#define sp  1
 77 
#define sp  1
82 
 
 78 
 
83 
/* Floating Point Registers (FPRs) */
 79 
/* Floating Point Registers (FPRs) */
84 
#define fr0 0
 80 
#define fr0     0
85 
#define fr1 1
 81 
#define fr1     1
86 
#define fr2 2
 82 
#define fr2     2
87 
#define fr3 3
 83 
#define fr3     3
88 
#define fr4 4
 84 
#define fr4     4
89 
#define fr5 5
 85 
#define fr5     5
90 
#define fr6 6
 86 
#define fr6     6
91 
#define fr7 7
 87 
#define fr7     7
92 
#define fr8 8
 88 
#define fr8     8
93 
#define fr9 9
 89 
#define fr9     9
94 
#define fr10    10
 90 
#define fr10    10
95 
#define fr11    11
 91 
#define fr11    11
96 
#define fr12    12
 92 
#define fr12    12
97 
#define fr13    13
 93 
#define fr13    13
98 
#define fr14    14
 94 
#define fr14    14
Line 112... Line 108...
112 
#define fr28    28
 108 
#define fr28    28
113 
#define fr29    29
 109 
#define fr29    29
114 
#define fr30    30
 110 
#define fr30    30
115 
#define fr31    31
 111 
#define fr31    31
116 
 
 112 
 
117 
#define vr0 0
 113 
#define vr0     0
118 
#define vr1 1
 114 
#define vr1     1
119 
#define vr2 2
 115 
#define vr2     2
120 
#define vr3 3
 116 
#define vr3     3
121 
#define vr4 4
 117 
#define vr4     4
122 
#define vr5 5
 118 
#define vr5     5
123 
#define vr6 6
 119 
#define vr6     6
124 
#define vr7 7
 120 
#define vr7     7
125 
#define vr8 8
 121 
#define vr8     8
126 
#define vr9 9
 122 
#define vr9     9
127 
#define vr10    10
 123 
#define vr10    10
128 
#define vr11    11
 124 
#define vr11    11
129 
#define vr12    12
 125 
#define vr12    12
130 
#define vr13    13
 126 
#define vr13    13
131 
#define vr14    14
 127 
#define vr14    14
Line 179... Line 175...
179 
#define evr29   29
 175 
#define evr29   29
180 
#define evr30   30
 176 
#define evr30   30
181 
#define evr31   31
 177 
#define evr31   31
182 
 
 178 
 
183 
/* Special Purpose Registers (SPRs) */
 179 
/* Special Purpose Registers (SPRs) */
184 
#define xer 1
 180 
#define xer     1
185 
#define lr  8
 181 
#define lr      8
186 
#define ctr 9
 182 
#define ctr     9
187 
#define dec 22
 183 
#define dec     22
188 
#define srr0    26
 184 
#define srr0    26
189 
#define srr1    27
 185 
#define srr1    27
190 
#define sprg0   272
 186 
#define sprg0   272
191 
#define sprg1   273
 187 
#define sprg1   273
192 
#define sprg2   274
 188 
#define sprg2   274
193 
#define sprg3   275
 189 
#define sprg3   275
194 
#define prv 287
 190 
#define prv     287
195 
 
 - 
 
196 
.macro REGISTERS_STORE r
 - 
 
197 
    stw r0, 0(\r)
 - 
 
198 
    stw r1, 4(\r)
 - 
 
199 
    stw r2, 8(\r)
 - 
 
200 
    stw r3, 12(\r)
 - 
 
201 
    stw r4, 16(\r)
 - 
 
202 
    stw r5, 20(\r)
 - 
 
203 
    stw r6, 24(\r)
 - 
 
204 
    stw r7, 28(\r)
 - 
 
205 
    stw r8, 32(\r)
 - 
 
206 
    stw r9, 36(\r)
 - 
 
207 
    stw r10, 40(\r)
 - 
 
208 
    stw r11, 44(\r)
 - 
 
209 
    stw r12, 48(\r)
 - 
 
210 
    stw r13, 52(\r)
 - 
 
211 
    stw r14, 56(\r)
 - 
 
212 
    stw r15, 60(\r)
 - 
 
213 
    stw r16, 64(\r)
 - 
 
214 
    stw r17, 68(\r)
 - 
 
215 
    stw r18, 72(\r)
 - 
 
216 
    stw r19, 76(\r)
 - 
 
217 
    stw r20, 80(\r)
 - 
 
218 
    stw r21, 84(\r)
 - 
 
219 
    stw r22, 88(\r)
 - 
 
220 
    stw r23, 92(\r)
 - 
 
221 
    stw r24, 96(\r)
 - 
 
222 
    stw r25, 100(\r)
 - 
 
223 
    stw r26, 104(\r)
 - 
 
224 
    stw r27, 108(\r)
 - 
 
225 
    stw r28, 112(\r)
 - 
 
226 
    stw r29, 116(\r)
 - 
 
227 
    stw r30, 120(\r)
 - 
 
228 
    stw r31, 124(\r)
 - 
 
229 
.endm
 - 
 
230 
 
 - 
 
231 
.macro REGISTERS_LOAD r
 - 
 
232 
    lwz r0, 0(\r)
 - 
 
233 
    lwz r1, 4(\r)
 - 
 
234 
    lwz r2, 8(\r)  
 - 
 
235 
    lwz r3, 12(\r)
 - 
 
236 
    lwz r4, 16(\r)
 - 
 
237 
    lwz r5, 20(\r)
 - 
 
238 
    lwz r6, 24(\r)
 - 
 
239 
    lwz r7, 28(\r)
 - 
 
240 
    lwz r8, 32(\r)
 - 
 
241 
    lwz r9, 36(\r)
 - 
 
242 
    lwz r10, 40(\r)
 - 
 
243 
    lwz r11, 44(\r)
 - 
 
244 
    lwz r12, 48(\r)
 - 
 
245 
    lwz r13, 52(\r)
 - 
 
246 
    lwz r14, 56(\r)
 - 
 
247 
    lwz r15, 60(\r)
 - 
 
248 
    lwz r16, 64(\r)
 - 
 
249 
    lwz r17, 68(\r)
 - 
 
250 
    lwz r18, 72(\r)
 - 
 
251 
    lwz r19, 76(\r)
 - 
 
252 
    lwz r20, 80(\r)
 - 
 
253 
    lwz r21, 84(\r)
 - 
 
254 
    lwz r22, 88(\r)
 - 
 
255 
    lwz r23, 92(\r)
 - 
 
256 
    lwz r24, 96(\r)
 - 
 
257 
    lwz r25, 100(\r)
 - 
 
258 
    lwz r26, 104(\r)
 - 
 
259 
    lwz r27, 108(\r)
 - 
 
260 
    lwz r28, 112(\r)
 - 
 
261 
    lwz r29, 116(\r)
 - 
 
262 
    lwz r30, 120(\r)
 - 
 
263 
    lwz r31, 124(\r)
 - 
 
264 
.endm
 - 
 
265 
 
 191 
 
266 
#endif
 192 
#endif