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 *
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 *
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 * Page table layout:
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 * Page table layout:
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 * - 32-bit virtual addresses
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 * - 32-bit virtual addresses
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 * - Offset is 14 bits => pages are 16K long
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 * - Offset is 14 bits => pages are 16K long
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 * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long
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 * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long
- 
 
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 * - PTE's replace EntryLo v (valid) bit with p (present) bit
- 
 
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 * - PTE's use only one bit to distinguish between cacheable and uncacheable mappings
- 
 
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 * - PTE's define soft_valid field to ensure there is at least one 1 bit even if the p bit is cleared
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 * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed)
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 * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed)
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 * - PTL0 has 64 entries (6 bits)
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 * - PTL0 has 64 entries (6 bits)
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 * - PTL1 is not used
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 * - PTL1 is not used
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 * - PTL2 is not used
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 * - PTL2 is not used
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 * - PTL3 has 4096 entries (12 bits)
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 * - PTL3 has 4096 entries (12 bits)
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#define PTL2_INDEX_ARCH(vaddr)  0
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#define PTL2_INDEX_ARCH(vaddr)  0
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#define PTL3_INDEX_ARCH(vaddr)  (((vaddr)>>14)&0x3fff)
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#define PTL3_INDEX_ARCH(vaddr)  (((vaddr)>>14)&0x3fff)
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#define SET_PTL0_ADDRESS_ARCH(ptl0)
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#define SET_PTL0_ADDRESS_ARCH(ptl0)
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#define GET_PTL1_ADDRESS_ARCH(ptl0, i)      (((pte_t *)(ptl0))[(i)].lo.pfn<<12)
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#define GET_PTL1_ADDRESS_ARCH(ptl0, i)      (((pte_t *)(ptl0))[(i)].pfn<<12)
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#define GET_PTL2_ADDRESS_ARCH(ptl1, i)      (ptl1)
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#define GET_PTL2_ADDRESS_ARCH(ptl1, i)      (ptl1)
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#define GET_PTL3_ADDRESS_ARCH(ptl2, i)      (ptl2)
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#define GET_PTL3_ADDRESS_ARCH(ptl2, i)      (ptl2)
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#define GET_FRAME_ADDRESS_ARCH(ptl3, i)     (((pte_t *)(ptl3))[(i)].lo.pfn<<12)
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#define GET_FRAME_ADDRESS_ARCH(ptl3, i)     (((pte_t *)(ptl3))[(i)].pfn<<12)
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#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)   (((pte_t *)(ptl0))[(i)].lo.pfn = (a)>>12)
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#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)   (((pte_t *)(ptl0))[(i)].pfn = (a)>>12)
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#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)  (((pte_t *)(ptl3))[(i)].lo.pfn = (a)>>12)
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#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)  (((pte_t *)(ptl3))[(i)].pfn = (a)>>12)
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#define GET_PTL1_FLAGS_ARCH(ptl0, i)        get_pt_flags((pte_t *)(ptl0), (index_t)(i))
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#define GET_PTL1_FLAGS_ARCH(ptl0, i)        get_pt_flags((pte_t *)(ptl0), (index_t)(i))
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#define GET_PTL2_FLAGS_ARCH(ptl1, i)        PAGE_PRESENT
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#define GET_PTL2_FLAGS_ARCH(ptl1, i)        PAGE_PRESENT
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#define GET_PTL3_FLAGS_ARCH(ptl2, i)        PAGE_PRESENT
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#define GET_PTL3_FLAGS_ARCH(ptl2, i)        PAGE_PRESENT
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#define GET_FRAME_FLAGS_ARCH(ptl3, i)       get_pt_flags((pte_t *)(ptl3), (index_t)(i))
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#define GET_FRAME_FLAGS_ARCH(ptl3, i)       get_pt_flags((pte_t *)(ptl3), (index_t)(i))
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static inline int get_pt_flags(pte_t *pt, index_t i)
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static inline int get_pt_flags(pte_t *pt, index_t i)
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{
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{
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    pte_t *p = &pt[i];
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    pte_t *p = &pt[i];
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    return (
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    return (
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        ((p->lo.c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) |
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        (p->cacheable<<PAGE_CACHEABLE_SHIFT) |
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        ((!p->lo.v)<<PAGE_PRESENT_SHIFT) |
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        ((!p->p)<<PAGE_PRESENT_SHIFT) |
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        (1<<PAGE_USER_SHIFT) |
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        (1<<PAGE_USER_SHIFT) |
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        (1<<PAGE_READ_SHIFT) |
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        (1<<PAGE_READ_SHIFT) |
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        ((p->w)<<PAGE_WRITE_SHIFT) |
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        ((p->w)<<PAGE_WRITE_SHIFT) |
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        (1<<PAGE_EXEC_SHIFT) |
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        (1<<PAGE_EXEC_SHIFT) |
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        p->lo.g<<PAGE_GLOBAL_SHIFT
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        (p->g<<PAGE_GLOBAL_SHIFT)
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    );
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    );
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}
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}
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static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
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static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
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{
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{
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    pte_t *p = &pt[i];
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    pte_t *p = &pt[i];
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    p->lo.c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
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    p->cacheable = (flags & PAGE_CACHEABLE) != 0;
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    p->lo.v = !(flags & PAGE_NOT_PRESENT);
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    p->p = !(flags & PAGE_NOT_PRESENT);
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    p->lo.g = (flags & PAGE_GLOBAL) != 0;
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    p->g = (flags & PAGE_GLOBAL) != 0;
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    p->w = (flags & PAGE_WRITE) != 0;
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    p->w = (flags & PAGE_WRITE) != 0;
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    /*
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     * Ensure that valid entries have at least one bit set.
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     */
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    p->soft_valid = 1;
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}
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}
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extern void page_arch_init(void);
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extern void page_arch_init(void);
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#endif /* __ASM__ */
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#endif /* __ASM__ */