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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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#include <arch/mm/as.h>
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#include <arch/mm/as.h>
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#include <arch/mm/asid.h>
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#include <arch/mm/page.h>
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#include <genarch/mm/as_ht.h>
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#include <genarch/mm/as_ht.h>
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#include <genarch/mm/asid_fifo.h>
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#include <genarch/mm/asid_fifo.h>
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#include <mm/asid.h>
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#include <arch.h>
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#include <arch/barrier.h>
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#include <synch/spinlock.h>
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/** Architecture dependent address space init. */
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/** Architecture dependent address space init. */
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void as_arch_init(void)
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void as_arch_init(void)
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{
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{
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    as_operations = &as_ht_operations;
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    as_operations = &as_ht_operations;
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    asid_fifo_init();
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    asid_fifo_init();
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}
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}
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/** Prepare registers for switching to another address space.
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 *
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 * @param as Address space.
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 */
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void as_install_arch(as_t *as)
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{
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    ipl_t ipl;
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    region_register rr;
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    int i;
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    ipl = interrupts_disable();
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    spinlock_lock(&as->lock);
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    ASSERT(as->asid != ASID_INVALID);
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    /*
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     * Load respective ASID (7 consecutive RIDs) to
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     * region registers.
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     */
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    for (i = 0; i < REGION_REGISTERS; i++) {
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        if (i == VRN_KERNEL)
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            continue;
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        rr.word = rr_read(i);
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        rr.map.ve = false;          /* disable VHPT walker */
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        rr.map.rid = ASID2RID(as->asid, i);
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        rr.map.ps = PAGE_WIDTH;
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        rr_write(i, rr.word);
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    }
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    srlz_d();
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    srlz_i();
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    spinlock_unlock(&as->lock);
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    interrupts_restore(ipl);
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}