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#if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)
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#if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)
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#error Memory stack must be 16-byte aligned.
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#error Memory stack must be 16-byte aligned.
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#endif
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#endif
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- 
 
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/** Partitioning of bank 0 registers. */
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#define R_OFFS 		r16
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#define R_HANDLER	r17
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#define R_RET		r18
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#define R_KSTACK	r23	/* keep in sync with before_thread_runs_arch() */
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/** Heavyweight interrupt handler
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/** Heavyweight interrupt handler
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 *
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 *
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 * This macro roughly follows steps from 1 to 19 described in
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 * This macro roughly follows steps from 1 to 19 described in
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 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
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 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
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 *
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 *
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 * @param offs Offset from the beginning of IVT.
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 * @param offs Offset from the beginning of IVT.
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 * @param handler Interrupt handler address.
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 * @param handler Interrupt handler address.
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 */
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 */
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.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
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.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
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    .org ivt + \offs
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    .org ivt + \offs
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	mov r24 = \offs
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	mov R_OFFS = \offs
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	movl r25 = \handler ;;
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	movl R_HANDLER = \handler ;;
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	mov ar.k0 = r24
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	mov ar.k1 = r25
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	br heavyweight_handler
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	br heavyweight_handler
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.endm
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.endm
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.global heavyweight_handler
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.global heavyweight_handler
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heavyweight_handler:
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heavyweight_handler:
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    /* 1. copy interrupt registers into bank 0 */
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    /* 1. copy interrupt registers into bank 0 */
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	/*
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	 * Note that r24-r31 from bank0 can be used only as long as PSR.ic = 0.
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	 */
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	mov r24 = cr.iip
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	mov r24 = cr.iip
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	mov r25 = cr.ipsr
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	mov r25 = cr.ipsr
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	mov r26 = cr.iipa
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	mov r26 = cr.iipa
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	mov r27 = cr.isr
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	mov r27 = cr.isr
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	mov r28 = cr.ifa
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	mov r28 = cr.ifa
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	st8 [r31] = r29, -8	/* save ar.bsp */
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	st8 [r31] = r29, -8	/* save ar.bsp */
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	mov ar.rsc = r24	/* restore RSE's setting */
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	mov ar.rsc = r24	/* restore RSE's setting */
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    /* steps 6 - 15 are done by heavyweight_handler_inner() */
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    /* steps 6 - 15 are done by heavyweight_handler_inner() */
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	mov r24 = b0 		/* save b0 belonging to interrupted context */
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	mov R_RET = b0 		/* save b0 belonging to interrupted context */
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	mov r26 = ar.k0
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	mov r25 = ar.k1
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	br.call.sptk.many rp = heavyweight_handler_inner
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	br.call.sptk.many b0 = heavyweight_handler_inner
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0:	mov b0 = r24		/* restore b0 belonging to the interrupted context */
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0:	mov b0 = R_RET		/* restore b0 belonging to the interrupted context */
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    /* 16. RSE switch to interrupted context */
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    /* 16. RSE switch to interrupted context */
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	cover			/* allocate zerro size frame (step 1 (from Intel Docs)) */
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	cover			/* allocate zerro size frame (step 1 (from Intel Docs)) */
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	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
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	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
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	 * will be preserved in stacked registers and backing store.
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	 * will be preserved in stacked registers and backing store.
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	 */
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	 */
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	alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;
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	alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;
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	/* bank 0 is going to be shadowed, copy essential data from there */
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	/* bank 0 is going to be shadowed, copy essential data from there */
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	mov loc1 = r24	/* b0 belonging to interrupted context */
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	mov loc1 = R_RET	/* b0 belonging to interrupted context */
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	mov loc2 = r25
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	mov loc2 = R_HANDLER
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	mov out0 = r26
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	mov out0 = R_OFFS
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	add out1 = STACK_SCRATCH_AREA_SIZE, r12
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	add out1 = STACK_SCRATCH_AREA_SIZE, r12
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    /* 6. switch to bank 1 and reenable PSR.ic */
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    /* 6. switch to bank 1 and reenable PSR.ic */
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	ssm PSR_IC_MASK
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	ssm PSR_IC_MASK
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    /* 15. disable PSR.ic and switch to bank 0 */
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    /* 15. disable PSR.ic and switch to bank 0 */
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	rsm PSR_IC_MASK
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	rsm PSR_IC_MASK
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	bsw.0 ;;
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	bsw.0 ;;
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	srlz.d
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	srlz.d
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	mov r24 = loc1
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	mov R_RET = loc1
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	mov ar.pfs = loc0
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	mov ar.pfs = loc0
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	br.ret.sptk.many b0
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	br.ret.sptk.many b0
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.global ivt
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.global ivt
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.align 32768
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.align 32768