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Line 52... | Line 52... | ||
52 | /** Switch to userspace - low level code. |
52 | /** Switch to userspace - low level code. |
53 | * |
53 | * |
54 | * @param in0 Userspace entry point address. |
54 | * @param in0 Userspace entry point address. |
55 | * @param in1 Userspace stack pointer address. |
55 | * @param in1 Userspace stack pointer address. |
56 | * @param in2 Userspace register stack pointer address. |
56 | * @param in2 Userspace register stack pointer address. |
- | 57 | * @param in3 Userspace address of thread uspace_arg_t structure. |
|
57 | * @param in3 Value to be stored in IPSR. |
58 | * @param in4 Value to be stored in IPSR. |
58 | * @param in4 Value to be stored in RSC. |
59 | * @param in5 Value to be stored in RSC. |
59 | */ |
60 | */ |
60 | .global switch_to_userspace |
61 | .global switch_to_userspace |
61 | switch_to_userspace: |
62 | switch_to_userspace: |
62 | alloc loc0 = ar.pfs, 5, 3, 0, 0 |
63 | alloc loc0 = ar.pfs, 6, 3, 0, 0 |
63 | rsm (PSR_IC_MASK | PSR_I_MASK) /* disable interruption collection and interrupts */ |
64 | rsm (PSR_IC_MASK | PSR_I_MASK) /* disable interruption collection and interrupts */ |
64 | srlz.d ;; |
65 | srlz.d ;; |
65 | srlz.i ;; |
66 | srlz.i ;; |
66 | 67 | ||
67 | mov cr.ipsr = in3 |
68 | mov cr.ipsr = in4 |
68 | mov cr.iip = in0 |
69 | mov cr.iip = in0 |
69 | mov r12 = in1 |
70 | mov r12 = in1 |
70 | 71 | ||
71 | xor r1 = r1, r1 |
72 | xor r1 = r1, r1 |
72 | 73 | ||
Line 82... | Line 83... | ||
82 | mov ar.rsc = loc1 ;; /* put RSE into enforced lazy mode */ |
83 | mov ar.rsc = loc1 ;; /* put RSE into enforced lazy mode */ |
83 | 84 | ||
84 | flushrs ;; |
85 | flushrs ;; |
85 | 86 | ||
86 | mov ar.bspstore = in2 ;; |
87 | mov ar.bspstore = in2 ;; |
87 | mov ar.rsc = in4 ;; |
88 | mov ar.rsc = in5 ;; |
- | 89 | ||
- | 90 | mov r8 = in3 |
|
88 | 91 | ||
89 | rfi ;; |
92 | rfi ;; |