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    __asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
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    __asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
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    return v;
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    return v;
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}
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}
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/** Return Processor State Register.
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 *
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 * @return PSR.
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 */
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static inline __u64 psr_read(void)
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{
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    __u64 v;
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    __asm__ volatile ("mov %0 = psr\n" : "=r" (v));
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    return v;
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}
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/** Read IVA (Interruption Vector Address).
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/** Read IVA (Interruption Vector Address).
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 *
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 *
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 * @return Return location of interruption vector table.
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 * @return Return location of interruption vector table.
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 */
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 */
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static inline __u64 iva_read(void)
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static inline __u64 iva_read(void)
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 *
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 *
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 * @return PSR.
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 * @return PSR.
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 */
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 */
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static inline ipl_t interrupts_read(void)
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static inline ipl_t interrupts_read(void)
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{
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{
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    __u64 v;
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    __asm__ volatile ("mov %0 = psr\n" : "=r" (v));
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    return (ipl_t) v;
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    return (ipl_t) psr_read();
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}
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}
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/** Disable protection key checking. */
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/** Disable protection key checking. */
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static inline void pk_disable(void)
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static inline void pk_disable(void)
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{
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{
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extern void cpu_halt(void);
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extern void cpu_halt(void);
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extern void cpu_sleep(void);
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extern void cpu_sleep(void);
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extern void asm_delay_loop(__u32 t);
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extern void asm_delay_loop(__u32 t);
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extern void switch_to_userspace(__address entry, __address sp, __address bsp, __u64 ipsr, __u64 rsc);
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#endif
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#endif