WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia32/src/smp/apic.c



 *
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
 * optimize the code too much and accesses to l_apic and io_apic, that must
 * always be 32-bit, would use byte oriented instructions.
 */
volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
 
uint32_t apic_id_mask = 0;
 
static int apic_poll_errors(void);
 
#ifdef LAPIC_VERBOSE
static char *delmod_str[] = {

 *
 * @param vector Interrupt vector to be sent.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_broadcast_custom_ipi(uint8_t vector)
{
    icr_t icr;
 
    icr.lo = l_apic[ICRlo];
    icr.delmod = DELMOD_FIXED;

 *
 * @param apicid APIC ID of the processor to be brought up.
 *
 * @return 0 on failure, 1 on success.
 */
int l_apic_send_init_ipi(uint8_t apicid)
{
    icr_t icr;
    int i;
 
    /*

        /*
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
         */
        for (i = 0; i<2; i++) {
            icr.lo = l_apic[ICRlo];
            icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */
            icr.delmod = DELMOD_STARTUP;
            icr.destmod = DESTMOD_PHYS;
            icr.level = LEVEL_ASSERT;
            icr.shorthand = SHORTHAND_NONE;
            icr.trigger_mode = TRIGMOD_LEVEL;

    icr_t icr;
    tdcr_t tdcr;
    lvt_tm_t tm;
    ldr_t ldr;
    dfr_t dfr;
    uint32_t t1, t2;
 
    /* Initialize LVT Error register. */
    error.value = l_apic[LVT_Err];
    error.masked = true;
    l_apic[LVT_Err] = error.value;

 
/** Get Local APIC ID.
 *
 * @return Local APIC ID.
 */
uint8_t l_apic_id(void)
{
    l_apic_id_t idreg;
   
    idreg.value = l_apic[L_APIC_ID];
    return idreg.apic_id;

 *
 * @param address IO APIC register address.
 *
 * @return Content of the addressed IO APIC register.
 */
uint32_t io_apic_read(uint8_t address)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;

/** Write to IO APIC register.
 *
 * @param address IO APIC register address.
 * @param x Content to be written to the addressed IO APIC register.
 */
void io_apic_write(uint8_t address, uint32_t x)
{
    io_regsel_t regsel;
   
    regsel.value = io_apic[IOREGSEL];
    regsel.reg_addr = address;

 * @param pin IO APIC pin number.
 * @param dest Interrupt destination address.
 * @param v Interrupt vector to trigger.
 * @param flags Flags.
 */
void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags)
{
    io_redirection_reg_t reg;
    int dlvr = DELMOD_FIXED;
   
    if (flags & LOPRI)

 
/** Mask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
 */
void io_apic_disable_irqs(uint16_t irqmask)
{
    io_redirection_reg_t reg;
    int i, pin;
   
    for (i=0;i<16;i++) {

 
/** Unmask IRQs in IO APIC.
 *
 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
 */
void io_apic_enable_irqs(uint16_t irqmask)
{
    int i, pin;
    io_redirection_reg_t reg;  
   
    for (i=0;i<16;i++) {

Rev 1708	Rev 1780
Line 65...	Line 65...
65	*	65	*
66	* Pay special attention to the volatile keyword. Without it, gcc -O2 would	66	* Pay special attention to the volatile keyword. Without it, gcc -O2 would
67	* optimize the code too much and accesses to l_apic and io_apic, that must	67	* optimize the code too much and accesses to l_apic and io_apic, that must
68	* always be 32-bit, would use byte oriented instructions.	68	* always be 32-bit, would use byte oriented instructions.
69	*/	69	*/
70	volatile __u32 l_apic = (__u32 ) 0xfee00000;	70	volatile uint32_t l_apic = (uint32_t ) 0xfee00000;
71	volatile __u32 io_apic = (__u32 ) 0xfec00000;	71	volatile uint32_t io_apic = (uint32_t ) 0xfec00000;
72		72
73	__u32 apic_id_mask = 0;	73	uint32_t apic_id_mask = 0;
74		74
75	static int apic_poll_errors(void);	75	static int apic_poll_errors(void);
76		76
77	#ifdef LAPIC_VERBOSE	77	#ifdef LAPIC_VERBOSE
78	static char *delmod_str[] = {	78	static char *delmod_str[] = {
Line 216...	Line 216...
216	*	216	*
217	* @param vector Interrupt vector to be sent.	217	* @param vector Interrupt vector to be sent.
218	*	218	*
219	* @return 0 on failure, 1 on success.	219	* @return 0 on failure, 1 on success.
220	*/	220	*/
221	int l_apic_broadcast_custom_ipi(__u8 vector)	221	int l_apic_broadcast_custom_ipi(uint8_t vector)
222	{	222	{
223	icr_t icr;	223	icr_t icr;
224		224
225	icr.lo = l_apic[ICRlo];	225	icr.lo = l_apic[ICRlo];
226	icr.delmod = DELMOD_FIXED;	226	icr.delmod = DELMOD_FIXED;
Line 246...	Line 246...
246	*	246	*
247	* @param apicid APIC ID of the processor to be brought up.	247	* @param apicid APIC ID of the processor to be brought up.
248	*	248	*
249	* @return 0 on failure, 1 on success.	249	* @return 0 on failure, 1 on success.
250	*/	250	*/
251	int l_apic_send_init_ipi(__u8 apicid)	251	int l_apic_send_init_ipi(uint8_t apicid)
252	{	252	{
253	icr_t icr;	253	icr_t icr;
254	int i;	254	int i;
255		255
256	/*	256	/*
Line 303...	Line 303...
303	/*	303	/*
304	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.	304	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
305	*/	305	*/
306	for (i = 0; i<2; i++) {	306	for (i = 0; i<2; i++) {
307	icr.lo = l_apic[ICRlo];	307	icr.lo = l_apic[ICRlo];
308	icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */	308	icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */
309	icr.delmod = DELMOD_STARTUP;	309	icr.delmod = DELMOD_STARTUP;
310	icr.destmod = DESTMOD_PHYS;	310	icr.destmod = DESTMOD_PHYS;
311	icr.level = LEVEL_ASSERT;	311	icr.level = LEVEL_ASSERT;
312	icr.shorthand = SHORTHAND_NONE;	312	icr.shorthand = SHORTHAND_NONE;
313	icr.trigger_mode = TRIGMOD_LEVEL;	313	icr.trigger_mode = TRIGMOD_LEVEL;
Line 329...	Line 329...
329	icr_t icr;	329	icr_t icr;
330	tdcr_t tdcr;	330	tdcr_t tdcr;
331	lvt_tm_t tm;	331	lvt_tm_t tm;
332	ldr_t ldr;	332	ldr_t ldr;
333	dfr_t dfr;	333	dfr_t dfr;
334	__u32 t1, t2;	334	uint32_t t1, t2;
335		335
336	/* Initialize LVT Error register. */	336	/* Initialize LVT Error register. */
337	error.value = l_apic[LVT_Err];	337	error.value = l_apic[LVT_Err];
338	error.masked = true;	338	error.masked = true;
339	l_apic[LVT_Err] = error.value;	339	l_apic[LVT_Err] = error.value;
Line 453...	Line 453...
453		453
454	/** Get Local APIC ID.	454	/** Get Local APIC ID.
455	*	455	*
456	* @return Local APIC ID.	456	* @return Local APIC ID.
457	*/	457	*/
458	__u8 l_apic_id(void)	458	uint8_t l_apic_id(void)
459	{	459	{
460	l_apic_id_t idreg;	460	l_apic_id_t idreg;
461		461
462	idreg.value = l_apic[L_APIC_ID];	462	idreg.value = l_apic[L_APIC_ID];
463	return idreg.apic_id;	463	return idreg.apic_id;
Line 467...	Line 467...
467	*	467	*
468	* @param address IO APIC register address.	468	* @param address IO APIC register address.
469	*	469	*
470	* @return Content of the addressed IO APIC register.	470	* @return Content of the addressed IO APIC register.
471	*/	471	*/
472	__u32 io_apic_read(__u8 address)	472	uint32_t io_apic_read(uint8_t address)
473	{	473	{
474	io_regsel_t regsel;	474	io_regsel_t regsel;
475		475
476	regsel.value = io_apic[IOREGSEL];	476	regsel.value = io_apic[IOREGSEL];
477	regsel.reg_addr = address;	477	regsel.reg_addr = address;
Line 482...	Line 482...
482	/** Write to IO APIC register.	482	/** Write to IO APIC register.
483	*	483	*
484	* @param address IO APIC register address.	484	* @param address IO APIC register address.
485	* @param x Content to be written to the addressed IO APIC register.	485	* @param x Content to be written to the addressed IO APIC register.
486	*/	486	*/
487	void io_apic_write(__u8 address, __u32 x)	487	void io_apic_write(uint8_t address, uint32_t x)
488	{	488	{
489	io_regsel_t regsel;	489	io_regsel_t regsel;
490		490
491	regsel.value = io_apic[IOREGSEL];	491	regsel.value = io_apic[IOREGSEL];
492	regsel.reg_addr = address;	492	regsel.reg_addr = address;
Line 499...	Line 499...
499	* @param pin IO APIC pin number.	499	* @param pin IO APIC pin number.
500	* @param dest Interrupt destination address.	500	* @param dest Interrupt destination address.
501	* @param v Interrupt vector to trigger.	501	* @param v Interrupt vector to trigger.
502	* @param flags Flags.	502	* @param flags Flags.
503	*/	503	*/
504	void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)	504	void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags)
505	{	505	{
506	io_redirection_reg_t reg;	506	io_redirection_reg_t reg;
507	int dlvr = DELMOD_FIXED;	507	int dlvr = DELMOD_FIXED;
508		508
509	if (flags & LOPRI)	509	if (flags & LOPRI)
Line 525...	Line 525...
525		525
526	/** Mask IRQs in IO APIC.	526	/** Mask IRQs in IO APIC.
527	*	527	*
528	* @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).	528	* @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
529	*/	529	*/
530	void io_apic_disable_irqs(__u16 irqmask)	530	void io_apic_disable_irqs(uint16_t irqmask)
531	{	531	{
532	io_redirection_reg_t reg;	532	io_redirection_reg_t reg;
533	int i, pin;	533	int i, pin;
534		534
535	for (i=0;i<16;i++) {	535	for (i=0;i<16;i++) {
Line 551...	Line 551...
551		551
552	/** Unmask IRQs in IO APIC.	552	/** Unmask IRQs in IO APIC.
553	*	553	*
554	* @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).	554	* @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
555	*/	555	*/
556	void io_apic_enable_irqs(__u16 irqmask)	556	void io_apic_enable_irqs(uint16_t irqmask)
557	{	557	{
558	int i, pin;	558	int i, pin;
559	io_redirection_reg_t reg;	559	io_redirection_reg_t reg;
560		560
561	for (i=0;i<16;i++) {	561	for (i=0;i<16;i++) {

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/ia32/src/smp/apic.c @ 1784 – Rev 1708 → 1780