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| Rev 1189 | Rev 1251 | ||
|---|---|---|---|
| Line 197... | Line 197... | ||
| 197 | 197 | ||
| 198 | tss_initialize(tss_p); |
198 | tss_initialize(tss_p); |
| 199 | 199 | ||
| 200 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; |
200 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; |
| 201 | gdt_p[TSS_DES].special = 1; |
201 | gdt_p[TSS_DES].special = 1; |
| 202 | gdt_p[TSS_DES].granularity = 1; |
202 | gdt_p[TSS_DES].granularity = 0; |
| 203 | 203 | ||
| 204 | gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p); |
204 | gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p); |
| 205 | gdt_setlimit(&gdt_p[TSS_DES], sizeof(tss_t) - 1); |
205 | gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1); |
| 206 | 206 | ||
| 207 | /* |
207 | /* |
| 208 | * As of this moment, the current CPU has its own GDT pointing |
208 | * As of this moment, the current CPU has its own GDT pointing |
| 209 | * to its own TSS. We just need to load the TR register. |
209 | * to its own TSS. We just need to load the TR register. |
| 210 | */ |
210 | */ |
| 211 | tr_load(selector(TSS_DES)); |
211 | tr_load(selector(TSS_DES)); |
| 212 | 212 | ||
| 213 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */ |
213 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */ |
| 214 | clean_AM_flag(); /* Disable alignment check */ |
214 | clean_AM_flag(); /* Disable alignment check */ |
| 215 | } |
215 | } |
| 216 | 216 | ||
| 217 | void set_tls_desc(__address tls) |
217 | void set_tls_desc(__address tls) |
| 218 | { |
218 | { |