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Line 92... Line 92...
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#define DELIVS_PENDING  0x1
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#define DELIVS_PENDING  0x1
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/** Destination masks. */
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/** Destination masks. */
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#define DEST_ALL    0xff
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#define DEST_ALL    0xff
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/** Dest format models. */
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#define MODEL_FLAT  0xf
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#define MODEL_CLUSTER   0x0
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/** Interrupt Command Register. */
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/** Interrupt Command Register. */
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#define ICRlo       (0x300/sizeof(__u32))
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#define ICRlo       (0x300/sizeof(__u32))
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#define ICRhi       (0x310/sizeof(__u32))
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#define ICRhi       (0x310/sizeof(__u32))
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struct icr {
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struct icr {
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    union {
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    union {
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#define LAVR_Mask   0xff
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#define LAVR_Mask   0xff
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#define is_local_apic(x)    (((x)&LAVR_Mask&0xf0)==0x1)
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#define is_local_apic(x)    (((x)&LAVR_Mask&0xf0)==0x1)
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#define is_82489DX_apic(x)  ((((x)&LAVR_Mask&0xf0)==0x0))
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#define is_82489DX_apic(x)  ((((x)&LAVR_Mask&0xf0)==0x0))
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#define is_local_xapic(x)   (((x)&LAVR_Mask)==0x14)
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#define is_local_xapic(x)   (((x)&LAVR_Mask)==0x14)
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/** Logical Destination Register. */
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#define  LDR        (0x0d0/sizeof(__u32))
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union ldr {
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    __u32 value;
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    struct {
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        unsigned : 24;      /**< Reserver. */
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        __u8 id;        /**< Logical APIC ID. */
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    } __attribute__ ((packed));
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};
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typedef union ldr ldr_t;
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/** Destination Format Register. */
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#define DFR     (0x0e0/sizeof(__u32))
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union dfr {
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    __u32 value;
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    struct {
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        unsigned : 28;      /**< Reserved, all ones. */
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        unsigned model : 4; /**< Model. */
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    } __attribute__ ((packed));
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};
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typedef union dfr dfr_t;
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/* IO APIC */
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/* IO APIC */
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#define IOREGSEL    (0x00/sizeof(__u32))
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#define IOREGSEL    (0x00/sizeof(__u32))
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#define IOWIN       (0x10/sizeof(__u32))
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#define IOWIN       (0x10/sizeof(__u32))
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#define IOAPICID    0x00
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#define IOAPICID    0x00