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Line 69... Line 69...
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/** Interrupt Input Pin Polarities. */
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/** Interrupt Input Pin Polarities. */
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#define POLARITY_HIGH   0x0
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#define POLARITY_HIGH   0x0
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#define POLARITY_LOW    0x1
 72 
#define POLARITY_LOW    0x1
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 73 
 
- 
 
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/** Divide Values. (Bit 2 is always 0) */
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#define DIVIDE_2    0x0
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#define DIVIDE_4    0x1
- 
 
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#define DIVIDE_8    0x2
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#define DIVIDE_16   0x3
- 
 
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#define DIVIDE_32   0x8
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#define DIVIDE_64   0x9
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#define DIVIDE_128  0xa
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#define DIVIDE_1    0xb
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- 
 
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/** Timer Modes. */
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#define TIMER_ONESHOT   0x0
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#define TIMER_PERIODIC  0x1
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#define SEND_PENDING    (1<<12)
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#define SEND_PENDING    (1<<12)
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/** Interrupt Command Register. */
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/** Interrupt Command Register. */
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#define ICRlo       (0x300/sizeof(__u32))
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#define ICRlo       (0x300/sizeof(__u32))
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#define ICRhi       (0x310/sizeof(__u32))
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#define ICRhi       (0x310/sizeof(__u32))
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typedef struct icr icr_t;
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typedef struct icr icr_t;
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/* End Of Interrupt */
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/* End Of Interrupt */
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#define EOI     (0x0b0/sizeof(__u32))
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#define EOI     (0x0b0/sizeof(__u32))
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/* Error Status Register */
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/** Error Status Register. */
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#define ESR     (0x280/sizeof(__u32))
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#define ESR     (0x280/sizeof(__u32))
- 
 
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union esr {
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    __u32 value;
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    __u8 err_bitmap;
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    struct {
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        unsigned send_checksum_error : 1;
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        unsigned receive_checksum_error : 1;
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        unsigned send_accept_error : 1;
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        unsigned receive_accept_error : 1;
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        unsigned : 1;
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        unsigned send_illegal_vector : 1;
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        unsigned received_illegal_vector : 1;
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#define ESRClear    ((0xffffff<<8)|(1<<4))
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        unsigned illegal_register_address : 1;
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        unsigned : 24;
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    } __attribute__ ((packed));
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};
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typedef union esr esr_t;
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/* Task Priority Register */
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/* Task Priority Register */
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#define TPR     (0x080/sizeof(__u32))
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#define TPR     (0x080/sizeof(__u32))
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#define TPRClear    0xffffff00
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#define TPRClear    0xffffff00
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        unsigned : 22;          /**< Reserved. */
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        unsigned : 22;          /**< Reserved. */
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    } __attribute__ ((packed));
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    } __attribute__ ((packed));
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};
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};
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typedef union svr svr_t;
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typedef union svr svr_t;
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/* Time Divide Configuration Register */
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/** Time Divide Configuration Register. */
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#define TDCR        (0x3e0/sizeof(__u32))
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#define TDCR        (0x3e0/sizeof(__u32))
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union tdcr {
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    __u32 value;
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    struct {
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        unsigned div_value : 4;     /**< Divide Value, bit 2 is always 0. */
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        unsigned : 28;          /**< Reserved. */
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    } __attribute__ ((packed));
- 
 
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};
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#define TDCRClear   (~0xb)
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typedef union tdcr tdcr_t;
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/* Initial Count Register for Timer */
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/* Initial Count Register for Timer */
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#define ICRT        (0x380/sizeof(__u32))
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#define ICRT        (0x380/sizeof(__u32))
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/* Current Count Register for Timer */
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/* Current Count Register for Timer */
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#define CCRT        (0x390/sizeof(__u32))
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#define CCRT        (0x390/sizeof(__u32))
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/** Timer Modes. */
 - 
 
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#define TIMER_ONESHOT   0x0
 - 
 
141 
#define TIMER_PERIODIC  0x1
 - 
 
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 - 
 
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/** LVT Timer register. */
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/** LVT Timer register. */
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#define LVT_Tm      (0x320/sizeof(__u32))
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#define LVT_Tm      (0x320/sizeof(__u32))
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union lvt_tm {
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union lvt_tm {
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    __u32 value;
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    __u32 value;
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    struct {
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    struct {
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        unsigned : 15;      /**< Reserved. */
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        unsigned : 15;      /**< Reserved. */
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    } __attribute__ ((packed));
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    } __attribute__ ((packed));
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};
 222 
};
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typedef union lvt_error lvt_error_t;
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typedef union lvt_error lvt_error_t;
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193 
 
 - 
 
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#define LVT_PCINT   (0x340/sizeof(__u32))
 - 
 
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 - 
 
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/* Local APIC ID Register */
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/** Local APIC ID Register. */
197 
#define L_APIC_ID   (0x020/sizeof(__u32))
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#define L_APIC_ID   (0x020/sizeof(__u32))
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union lapic_id {
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    __u32 value;
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    struct {
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#define L_APIC_IDClear  (~(0xf<<24))
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        unsigned : 24;      /**< Reserved. */
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        __u8 apic_id;       /**< Local APIC ID. */
199 
#define L_APIC_IDShift  24
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    } __attribute__ ((packed));
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};
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#define L_APIC_IDMask   0xf
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typedef union lapic_id lapic_id_t;
201 
 
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202 
/* Local APIC Version Register */
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/* Local APIC Version Register */
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#define LAVR        (0x030/sizeof(__u32))
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#define LAVR        (0x030/sizeof(__u32))
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#define LAVR_Mask   0xff
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#define LAVR_Mask   0xff
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#define is_local_apic(x)    (((x)&LAVR_Mask&0xf0)==0x1)
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#define is_local_apic(x)    (((x)&LAVR_Mask&0xf0)==0x1)
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#define IOAPICID    0x00
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#define IOAPICID    0x00
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#define IOAPICVER   0x01
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#define IOAPICVER   0x01
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#define IOAPICARB   0x02
 249 
#define IOAPICARB   0x02
216 
#define IOREDTBL    0x10
 250 
#define IOREDTBL    0x10
217 
 
 251 
 
- 
 
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/** I/O Register Select Register. */
- 
 
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union io_regsel {
- 
 
 254 
    __u32 value;
- 
 
 255 
    struct {
- 
 
 256 
        __u8 reg_addr;      /**< APIC Register Address. */
- 
 
 257 
        unsigned : 24;      /**< Reserved. */
- 
 
 258 
    } __attribute__ ((packed));
- 
 
 259 
};
- 
 
 260 
typedef union io_regsel io_regsel_t;
- 
 
 261 
 
218 
/** I/O Redirection Register. */
 262 
/** I/O Redirection Register. */
219 
struct io_redirection_reg {
 263 
struct io_redirection_reg {
220 
    union {
 264 
    union {
221 
        __u32 lo;
 265 
        __u32 lo;
222 
        struct {
 266 
        struct {
Line 259... Line 303...
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extern void l_apic_timer_interrupt(__u8 n, __native stack[]);
 303 
extern void l_apic_timer_interrupt(__u8 n, __native stack[]);
260 
extern __u8 l_apic_id(void);
 304 
extern __u8 l_apic_id(void);
261 
 
 305 
 
262 
extern __u32 io_apic_read(__u8 address);
 306 
extern __u32 io_apic_read(__u8 address);
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extern void io_apic_write(__u8 address , __u32 x);
 307 
extern void io_apic_write(__u8 address , __u32 x);
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extern void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags);
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extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags);
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extern void io_apic_disable_irqs(__u16 irqmask);
 309 
extern void io_apic_disable_irqs(__u16 irqmask);
266 
extern void io_apic_enable_irqs(__u16 irqmask);
 310 
extern void io_apic_enable_irqs(__u16 irqmask);
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 311 
 
268 
#endif
 312 
#endif