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 */
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 */
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#ifndef __ia32_ASM_H__
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#ifndef __ia32_ASM_H__
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#define __ia32_ASM_H__
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#define __ia32_ASM_H__
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#include <arch/pm.h>
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#include <arch/types.h>
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#include <arch/types.h>
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#include <config.h>
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#include <config.h>
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extern __u32 interrupt_handler_size;
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extern __u32 interrupt_handler_size;
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static inline void invlpg(__address addr)
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static inline void invlpg(__address addr)
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{
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{
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    __asm__ volatile ("invlpg %0\n" :: "m" (*(__native *)addr));
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    __asm__ volatile ("invlpg %0\n" :: "m" (*(__native *)addr));
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}
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}
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/** Load GDTR register from memory.
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 *
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 * @param gdtr_reg Address of memory from where to load GDTR.
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 */
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static inline void gdtr_load(struct ptr_16_32 *gdtr_reg)
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{
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    __asm__ volatile ("lgdt %0\n" : : "m" (*gdtr_reg));
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}
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/** Store GDTR register to memory.
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 *
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 * @param gdtr_reg Address of memory to where to load GDTR.
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 */
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static inline void gdtr_store(struct ptr_16_32 *gdtr_reg)
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{
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    __asm__ volatile ("sgdt %0\n" : : "m" (*gdtr_reg));
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}
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/** Load IDTR register from memory.
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 *
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 * @param idtr_reg Address of memory from where to load IDTR.
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 */
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static inline void idtr_load(struct ptr_16_32 *idtr_reg)
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{
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    __asm__ volatile ("lidt %0\n" : : "m" (*idtr_reg));
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}
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/** Load TR from descriptor table.
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 *
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 * @param sel Selector specifying descriptor of TSS segment.
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 */
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static inline void tr_load(__u16 sel)
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{
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    __asm__ volatile ("ltr %0" : : "r" (sel));
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}
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#endif
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#endif