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 * Halt the current CPU until interrupt event.
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 * Halt the current CPU until interrupt event.
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 */
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 */
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static inline void cpu_halt(void) { __asm__("hlt\n"); };
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static inline void cpu_halt(void) { __asm__("hlt\n"); };
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static inline void cpu_sleep(void) { __asm__("hlt\n"); };
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static inline void cpu_sleep(void) { __asm__("hlt\n"); };
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/** Read CR2
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#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
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 *
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    { \
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 * Return value in CR2
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    __native res; \
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 *
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- 
 
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    __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
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 * @return Value read.
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    return res; \
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 */
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    }
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static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }
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/** Write CR3
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 *
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 * Write value to CR3.
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#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \
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 *
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    { \
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 * @param v Value to be written.
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    __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
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 */
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    }
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static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
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GEN_READ_REG(cr0);
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GEN_READ_REG(cr2);
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/** Read CR3
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GEN_READ_REG(cr3);
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GEN_WRITE_REG(cr3);
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 *
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- 
 
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GEN_READ_REG(dr0);
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GEN_READ_REG(dr1);
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GEN_READ_REG(dr2);
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GEN_READ_REG(dr3);
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GEN_READ_REG(dr6);
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 * Return value in CR3
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GEN_READ_REG(dr7);
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 *
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GEN_WRITE_REG(dr0);
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 * @return Value read.
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GEN_WRITE_REG(dr1);
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 */
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GEN_WRITE_REG(dr2);
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static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }
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GEN_WRITE_REG(dr3);
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GEN_WRITE_REG(dr6);
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GEN_WRITE_REG(dr7);
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/** Byte to port
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/** Byte to port
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 *
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 *
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 * Output byte to port
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 * Output byte to port
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 *
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 *