WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/src/pm.c/



 * There is no segmentation in long mode so we set up flat mode. In this
 * mode, we use, for each privilege level, two segments spanning the
 * whole memory. One is for code and one is for data.
 */
 
descriptor_t gdt[GDT_ITEMS] = {
    /* NULL descriptor */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    /* KTEXT descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,

     * on AMD64 it is 64-bit - 2 items in table */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
};
 
idescriptor_t idt[IDT_ITEMS];
 
ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (__u64) idt };
 
static tss_t tss;
tss_t *tss_p = NULL;
 
void gdt_tss_setbase(descriptor_t *d, __address base)
{
    tss_descriptor_t *td = (tss_descriptor_t *) d;
 
    td->base_0_15 = base & 0xffff;
    td->base_16_23 = ((base) >> 16) & 0xff;
    td->base_24_31 = ((base) >> 24) & 0xff;
    td->base_32_63 = ((base) >> 32);
}
 
void gdt_tss_setlimit(descriptor_t *d, __u32 limit)
{
    struct tss_descriptor *td = (tss_descriptor_t *) d;
 
    td->limit_0_15 = limit & 0xffff;
    td->limit_16_19 = (limit >> 16) & 0xf;
}
 
void idt_setoffset(idescriptor_t *d, __address offset)
{
    /*
     * Offset is a linear address.
     */
    d->offset_0_15 = offset & 0xffff;
    d->offset_16_31 = offset >> 16 & 0xffff;
    d->offset_32_63 = offset >> 32;
}
 
void tss_initialize(tss_t *t)
{
    memsetb((__address) t, sizeof(tss_t), 0);
}
 
/*
 * This function takes care of proper setup of IDT and IDTR.
 */
void idt_init(void)
{
    idescriptor_t *d;
    int i;
 
    for (i = 0; i < IDT_ITEMS; i++) {
        d = &idt[i];
 

/** Initialize segmentation - code/data/idt tables
 *
 */
void pm_init(void)
{
    descriptor_t *gdt_p = (struct descriptor *) gdtr.base;
    tss_descriptor_t *tss_desc;
 
    /*
     * Each CPU has its private GDT and TSS.
     * All CPUs share one IDT.
     */

         * the heap hasn't been initialized so far.
         */
        tss_p = &tss;
    }
    else {
        tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
        if (!tss_p)
            panic("could not allocate TSS\n");
    }
 
    tss_initialize(tss_p);
 
    tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
    tss_desc->present = 1;
    tss_desc->type = AR_TSS;
    tss_desc->dpl = PL_KERNEL;
   
    gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
    gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(tss_t) - 1);
 
    gdtr_load(&gdtr);
    idtr_load(&idtr);
    /*
     * As of this moment, the current CPU has its own GDT pointing

Rev 1186	Rev 1187
Line 44...	Line 44...
44	* There is no segmentation in long mode so we set up flat mode. In this	44	* There is no segmentation in long mode so we set up flat mode. In this
45	* mode, we use, for each privilege level, two segments spanning the	45	* mode, we use, for each privilege level, two segments spanning the
46	* whole memory. One is for code and one is for data.	46	* whole memory. One is for code and one is for data.
47	*/	47	*/
48		48
49	struct descriptor gdt[GDT_ITEMS] = {	49	descriptor_t gdt[GDT_ITEMS] = {
50	/* NULL descriptor */	50	/* NULL descriptor */
51	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	51	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
52	/* KTEXT descriptor */	52	/* KTEXT descriptor */
53	{ .limit_0_15 = 0xffff,	53	{ .limit_0_15 = 0xffff,
54	.base_0_15 = 0,	54	.base_0_15 = 0,
Line 108...	Line 108...
108	* on AMD64 it is 64-bit - 2 items in table */	108	* on AMD64 it is 64-bit - 2 items in table */
109	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	109	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
110	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }	110	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
111	};	111	};
112		112
113	struct idescriptor idt[IDT_ITEMS];	113	idescriptor_t idt[IDT_ITEMS];
114		114
115	struct ptr_16_64 gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };	115	ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
116	struct ptr_16_64 idtr = {.limit = sizeof(idt), .base= (__u64) idt };	116	ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (__u64) idt };
117		117
118	static struct tss tss;	118	static tss_t tss;
119	struct tss *tss_p = NULL;	119	tss_t *tss_p = NULL;
120		120
121	void gdt_tss_setbase(struct descriptor *d, __address base)	121	void gdt_tss_setbase(descriptor_t *d, __address base)
122	{	122	{
123	struct tss_descriptor td = (struct tss_descriptor ) d;	123	tss_descriptor_t td = (tss_descriptor_t ) d;
124		124
125	td->base_0_15 = base & 0xffff;	125	td->base_0_15 = base & 0xffff;
126	td->base_16_23 = ((base) >> 16) & 0xff;	126	td->base_16_23 = ((base) >> 16) & 0xff;
127	td->base_24_31 = ((base) >> 24) & 0xff;	127	td->base_24_31 = ((base) >> 24) & 0xff;
128	td->base_32_63 = ((base) >> 32);	128	td->base_32_63 = ((base) >> 32);
129	}	129	}
130		130
131	void gdt_tss_setlimit(struct descriptor *d, __u32 limit)	131	void gdt_tss_setlimit(descriptor_t *d, __u32 limit)
132	{	132	{
133	struct tss_descriptor td = (struct tss_descriptor ) d;	133	struct tss_descriptor td = (tss_descriptor_t ) d;
134		134
135	td->limit_0_15 = limit & 0xffff;	135	td->limit_0_15 = limit & 0xffff;
136	td->limit_16_19 = (limit >> 16) & 0xf;	136	td->limit_16_19 = (limit >> 16) & 0xf;
137	}	137	}
138		138
139	void idt_setoffset(struct idescriptor *d, __address offset)	139	void idt_setoffset(idescriptor_t *d, __address offset)
140	{	140	{
141	/*	141	/*
142	* Offset is a linear address.	142	* Offset is a linear address.
143	*/	143	*/
144	d->offset_0_15 = offset & 0xffff;	144	d->offset_0_15 = offset & 0xffff;
145	d->offset_16_31 = offset >> 16 & 0xffff;	145	d->offset_16_31 = offset >> 16 & 0xffff;
146	d->offset_32_63 = offset >> 32;	146	d->offset_32_63 = offset >> 32;
147	}	147	}
148		148
149	void tss_initialize(struct tss *t)	149	void tss_initialize(tss_t *t)
150	{	150	{
151	memsetb((__address) t, sizeof(struct tss), 0);	151	memsetb((__address) t, sizeof(tss_t), 0);
152	}	152	}
153		153
154	/*	154	/*
155	* This function takes care of proper setup of IDT and IDTR.	155	* This function takes care of proper setup of IDT and IDTR.
156	*/	156	*/
157	void idt_init(void)	157	void idt_init(void)
158	{	158	{
159	struct idescriptor *d;	159	idescriptor_t *d;
160	int i;	160	int i;
161		161
162	for (i = 0; i < IDT_ITEMS; i++) {	162	for (i = 0; i < IDT_ITEMS; i++) {
163	d = &idt[i];	163	d = &idt[i];
164		164
Line 181...	Line 181...
181	/** Initialize segmentation - code/data/idt tables	181	/** Initialize segmentation - code/data/idt tables
182	*	182	*
183	*/	183	*/
184	void pm_init(void)	184	void pm_init(void)
185	{	185	{
186	struct descriptor gdt_p = (struct descriptor ) gdtr.base;	186	descriptor_t gdt_p = (struct descriptor ) gdtr.base;
187	struct tss_descriptor *tss_desc;	187	tss_descriptor_t *tss_desc;
188		188
189	/*	189	/*
190	* Each CPU has its private GDT and TSS.	190	* Each CPU has its private GDT and TSS.
191	* All CPUs share one IDT.	191	* All CPUs share one IDT.
192	*/	192	*/
Line 198...	Line 198...
198	* the heap hasn't been initialized so far.	198	* the heap hasn't been initialized so far.
199	*/	199	*/
200	tss_p = &tss;	200	tss_p = &tss;
201	}	201	}
202	else {	202	else {
203	tss_p = (struct tss *) malloc(sizeof(struct tss),FRAME_ATOMIC);	203	tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
204	if (!tss_p)	204	if (!tss_p)
205	panic("could not allocate TSS\n");	205	panic("could not allocate TSS\n");
206	}	206	}
207		207
208	tss_initialize(tss_p);	208	tss_initialize(tss_p);
209		209
210	tss_desc = (struct tss_descriptor *) (&gdt_p[TSS_DES]);	210	tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
211	tss_desc->present = 1;	211	tss_desc->present = 1;
212	tss_desc->type = AR_TSS;	212	tss_desc->type = AR_TSS;
213	tss_desc->dpl = PL_KERNEL;	213	tss_desc->dpl = PL_KERNEL;
214		214
215	gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);	215	gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
216	gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);	216	gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(tss_t) - 1);
217		217
218	gdtr_load(&gdtr);	218	gdtr_load(&gdtr);
219	idtr_load(&idtr);	219	idtr_load(&idtr);
220	/*	220	/*
221	* As of this moment, the current CPU has its own GDT pointing	221	* As of this moment, the current CPU has its own GDT pointing

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/amd64/src/pm.c/ – Rev 1186 → 1187