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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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#define IREGISTER_SPACE 120
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#define IOFFSET_RAX 0x0
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#define IOFFSET_RBX 0x8
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#define IOFFSET_RCX 0x10
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#define IOFFSET_RDX 0x18
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#define IOFFSET_RSI 0x20
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#define IOFFSET_RDI 0x28
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#define IOFFSET_R8 0x30
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#define IOFFSET_R9 0x38
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#define IOFFSET_R10 0x40
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#define IOFFSET_R11 0x48
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#define IOFFSET_R12 0x50
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#define IOFFSET_R13 0x58
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#define IOFFSET_R14 0x60
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#define IOFFSET_R15 0x68
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#define IOFFSET_RBP 0x70
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#  Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
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#  Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
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# and 1 means interrupt with error word
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# and 1 means interrupt with error word
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#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
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#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
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#include <arch/pm.h>
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#include <arch/pm.h>
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#include <arch/context_offset.h>
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#include <arch/mm/page.h>
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#include <arch/mm/page.h>
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.text
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.text
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.global interrupt_handlers
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.global interrupt_handlers
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.global syscall_entry
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.global syscall_entry
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	movq IOFFSET_R12(%rsp), %r12
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	movq IOFFSET_R12(%rsp), %r12
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	movq IOFFSET_R13(%rsp), %r13
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	movq IOFFSET_R13(%rsp), %r13
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	movq IOFFSET_R14(%rsp), %r14
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	movq IOFFSET_R14(%rsp), %r14
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	movq IOFFSET_R15(%rsp), %r15
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	movq IOFFSET_R15(%rsp), %r15
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.endm
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.endm
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## Declare interrupt handlers
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## Declare interrupt handlers
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#
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#
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# Declare interrupt handlers for n interrupt
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# Declare interrupt handlers for n interrupt
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# vectors starting at vector i.
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# vectors starting at vector i.
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#
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#
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# The handlers setup data segment registers
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# and call exc_dispatch().
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# The handlers call exc_dispatch().
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#
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#
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.macro handler i n
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.macro handler i n
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	subq $IREGISTER_SPACE, %rsp
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	save_all_gpr
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	/*
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	movq $(\i),%rdi   # %rdi - first parameter
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	 * Choose between version with error code and version without error code.
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	movq %rsp, %rsi   # %rsi - pointer to interrupt_context
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	 * Both versions have to be of the same size. amd64 assembly is, however,
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	 * a little bit tricky. For instance, subq $0x80, %rsp and subq $0x78, %rsp
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	call exc_dispatch 	# exc_dispatch(i, stack)
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	 * can result in two instructions with different op-code lengths.
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	 * Therefore, pay special attention to the extra NOP's that serve as
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	 * a necessary fill.
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	 */
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	.iflt \i-32
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		.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST
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			/*
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# Test if this is interrupt with error word or not
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			 * Version with error word.
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	mov $\i,%cl;
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			 */
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			subq $IREGISTER_SPACE, %rsp
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			nop
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			nop
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			nop
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	movl $1,%eax;
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		.else
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			/*
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	test $0xe0,%cl;
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			 * Version without error word,
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	jnz 0f;
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			 */
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			subq $(IREGISTER_SPACE+8), %rsp
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	and $0x1f,%cl;
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		.endif
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	shl %cl,%eax;
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	.else
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		/*
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		 * Version without error word,
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		 */
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	and $ERROR_WORD_INTERRUPT_LIST,%eax;
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		subq $(IREGISTER_SPACE+8), %rsp
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	jz 0f;
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	.endif
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	save_all_gpr
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	movq $(\i), %rdi   	# %rdi - first parameter
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# Return with error word
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	movq %rsp, %rsi   	# %rsi - pointer to istate
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	call exc_dispatch 	# exc_dispatch(i, istate)
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	restore_all_gpr
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	restore_all_gpr
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	# $8 = Skip error word
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	# $8 = Skip error word
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	addq $IREGISTER_SPACE + 0x8, %rsp
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	iretq
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0:
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# Return with no error word
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	restore_all_gpr
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	addq $IREGISTER_SPACE, %rsp
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	addq $(IREGISTER_SPACE+8), %rsp
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	iretq
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	iretq
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	.if (\n-\i)-1
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	.if (\n-\i)-1
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	handler "(\i+1)",\n
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	handler "(\i+1)",\n
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	.endif
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	.endif