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 * part can be set only in CPL0 mode.
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 * part can be set only in CPL0 mode.
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 *
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 *
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 * The specs say, that on %fs:0 there is stored contents of %fs register,
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 * The specs say, that on %fs:0 there is stored contents of %fs register,
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 * we need not to go to CPL0 to read it.
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 * we need not to go to CPL0 to read it.
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 */
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 */
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__native sys_tls_set(__native addr)
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unative_t sys_tls_set(unative_t addr)
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{
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{
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    THREAD->arch.tls = addr;
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    THREAD->arch.tls = addr;
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    write_msr(AMD_MSR_FS, addr);
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    write_msr(AMD_MSR_FS, addr);
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    return 0;
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    return 0;
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}
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}