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#define __amd64_ATOMIC_H__
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#define __amd64_ATOMIC_H__
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#include <arch/types.h>
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#include <arch/types.h>
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#include <arch/barrier.h>
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#include <arch/barrier.h>
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#include <preemption.h>
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#include <preemption.h>
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typedef struct { volatile __u64 count; } atomic_t;
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static inline void atomic_set(atomic_t *val, __u64 i)
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{
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    val->count = i;
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}
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static inline __u64 atomic_get(atomic_t *val)
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{
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    return val->count;
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#include <typedefs.h>
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}
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static inline void atomic_inc(atomic_t *val) {
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static inline void atomic_inc(atomic_t *val) {
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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    __asm__ volatile ("lock incq %0\n" : "=m" (val->count));
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    __asm__ volatile ("lock incq %0\n" : "=m" (val->count));
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#else
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#else
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#else
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#else
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    __asm__ volatile ("decq %0\n" : "=m" (val->count));
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    __asm__ volatile ("decq %0\n" : "=m" (val->count));
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#endif /* CONFIG_SMP */
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#endif /* CONFIG_SMP */
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}
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}
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static inline count_t atomic_postinc(atomic_t *val)
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static inline long atomic_postinc(atomic_t *val)
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{
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{
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    count_t r;
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    long r;
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    __asm__ volatile (
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    __asm__ volatile (
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        "movq $1, %0\n"
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        "movq $1, %0\n"
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        "lock xaddq %0, %1\n"
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        "lock xaddq %0, %1\n"
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        : "=r" (r), "=m" (val->count)
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        : "=r" (r), "=m" (val->count)
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    );
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    );
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    return r;
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    return r;
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}
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}
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static inline count_t atomic_postdec(atomic_t *val)
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static inline long atomic_postdec(atomic_t *val)
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{
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{
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    count_t r;
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    long r;
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    __asm__ volatile (
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    __asm__ volatile (
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        "movq $-1, %0\n"
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        "movq $-1, %0\n"
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        "lock xaddq %0, %1\n"
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        "lock xaddq %0, %1\n"
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        : "=r" (r), "=m" (val->count)
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        : "=r" (r), "=m" (val->count)
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    return v;
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    return v;
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}
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}
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/** AMD64 specific fast spinlock */
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/** amd64 specific fast spinlock */
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static inline void atomic_lock_arch(atomic_t *val)
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static inline void atomic_lock_arch(atomic_t *val)
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{
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{
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    __u64 tmp;
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    __u64 tmp;
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    preemption_disable();
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    preemption_disable();
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#ifdef CONFIG_HT
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#ifdef CONFIG_HT
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        "pause;" /* Pentium 4's HT love this instruction */
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        "pause;" /* Pentium 4's HT love this instruction */
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#endif
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#endif
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        "mov %0, %1;"
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        "mov %0, %1;"
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        "testq %1, %1;"
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        "testq %1, %1;"
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        "jnz 0b;"       /* Leightweight looping on locked spinlock */
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        "jnz 0b;"       /* Lightweight looping on locked spinlock */
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        "incq %1;"      /* now use the atomic operation */
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        "incq %1;"      /* now use the atomic operation */
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        "xchgq %0, %1;"
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        "xchgq %0, %1;"
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        "testq %1, %1;"
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        "testq %1, %1;"
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        "jnz 0b;"
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        "jnz 0b;"