WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/amd64/include/asm.h



 
#include <arch/pm.h>
#include <arch/types.h>
#include <config.h>
 
extern void asm_delay_loop(uint32_t t);
extern void asm_fake_loop(uint32_t t);
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uintptr_t v;
   
    __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1)));
   
    return v;
}
 
static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };

 * Get byte from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Byte to port
 *
 * Output byte to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Swap Hidden part of GS register with visible one */
static inline void swapgs(void) { __asm__ volatile("swapgs"); }
 
/** Enable interrupts.

    );
    return v;
}
 
/** Write to MSR */
static inline void write_msr(uint32_t msr, uint64_t value)
{
    __asm__ volatile (
        "wrmsr;" : : "c" (msr),
        "a" ((uint32_t)(value)),
        "d" ((uint32_t)(value >> 32))
        );
}
 
static inline unative_t read_msr(uint32_t msr)
{
    uint32_t ax, dx;
 
    __asm__ volatile (
        "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
        );
    return ((uint64_t)dx << 32) | ax;
}
 
 
/** Enable local APIC
 *

        :
        :"%eax","%ecx","%edx"
        );
}
 
static inline uintptr_t * get_ip()
{
    uintptr_t *ip;
 
    __asm__ volatile (
        "mov %%rip, %0"
        : "=r" (ip)
        );

 
/** Invalidate TLB Entry.
 *
 * @param addr Address on a page whose TLB entry is to be invalidated.
 */
static inline void invlpg(uintptr_t addr)
{
    __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr)));
}
 
/** Load GDTR register from memory.
 *
 * @param gdtr_reg Address of memory from where to load GDTR.

 
/** Load TR from descriptor table.
 *
 * @param sel Selector specifying descriptor of TSS segment.
 */
static inline void tr_load(uint16_t sel)
{
    __asm__ volatile ("ltr %0" : : "r" (sel));
}
 
#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
    { \
    unative_t res; \
    __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
    return res; \
    }
 
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
    { \
    __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
    }
 
GEN_READ_REG(cr0);

Rev 1702	Rev 1780
Line 37...	Line 37...
37		37
38	#include <arch/pm.h>	38	#include <arch/pm.h>
39	#include <arch/types.h>	39	#include <arch/types.h>
40	#include <config.h>	40	#include <config.h>
41		41
42	extern void asm_delay_loop(__u32 t);	42	extern void asm_delay_loop(uint32_t t);
43	extern void asm_fake_loop(__u32 t);	43	extern void asm_fake_loop(uint32_t t);
44		44
45	/** Return base address of current stack.	45	/** Return base address of current stack.
46	*	46	*
47	* Return the base address of the current stack.	47	* Return the base address of the current stack.
48	* The stack is assumed to be STACK_SIZE bytes long.	48	* The stack is assumed to be STACK_SIZE bytes long.
49	* The stack must start on page boundary.	49	* The stack must start on page boundary.
50	*/	50	*/
51	static inline __address get_stack_base(void)	51	static inline uintptr_t get_stack_base(void)
52	{	52	{
53	__address v;	53	uintptr_t v;
54		54
55	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));	55	__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1)));
56		56
57	return v;	57	return v;
58	}	58	}
59		59
60	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };	60	static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
Line 66...	Line 66...
66	* Get byte from port	66	* Get byte from port
67	*	67	*
68	* @param port Port to read from	68	* @param port Port to read from
69	* @return Value read	69	* @return Value read
70	*/	70	*/
71	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }	71	static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
72		72
73	/** Byte to port	73	/** Byte to port
74	*	74	*
75	* Output byte to port	75	* Output byte to port
76	*	76	*
77	* @param port Port to write to	77	* @param port Port to write to
78	* @param val Value to write	78	* @param val Value to write
79	*/	79	*/
80	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }	80	static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
81		81
82	/** Swap Hidden part of GS register with visible one */	82	/** Swap Hidden part of GS register with visible one */
83	static inline void swapgs(void) { __asm__ volatile("swapgs"); }	83	static inline void swapgs(void) { __asm__ volatile("swapgs"); }
84		84
85	/** Enable interrupts.	85	/** Enable interrupts.
Line 147...	Line 147...
147	);	147	);
148	return v;	148	return v;
149	}	149	}
150		150
151	/** Write to MSR */	151	/** Write to MSR */
152	static inline void write_msr(__u32 msr, __u64 value)	152	static inline void write_msr(uint32_t msr, uint64_t value)
153	{	153	{
154	__asm__ volatile (	154	__asm__ volatile (
155	"wrmsr;" : : "c" (msr),	155	"wrmsr;" : : "c" (msr),
156	"a" ((__u32)(value)),	156	"a" ((uint32_t)(value)),
157	"d" ((__u32)(value >> 32))	157	"d" ((uint32_t)(value >> 32))
158	);	158	);
159	}	159	}
160		160
161	static inline __native read_msr(__u32 msr)	161	static inline unative_t read_msr(uint32_t msr)
162	{	162	{
163	__u32 ax, dx;	163	uint32_t ax, dx;
164		164
165	__asm__ volatile (	165	__asm__ volatile (
166	"rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)	166	"rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
167	);	167	);
168	return ((__u64)dx << 32) \| ax;	168	return ((uint64_t)dx << 32) \| ax;
169	}	169	}
170		170
171		171
172	/** Enable local APIC	172	/** Enable local APIC
173	*	173	*
Line 185...	Line 185...
185	:	185	:
186	:"%eax","%ecx","%edx"	186	:"%eax","%ecx","%edx"
187	);	187	);
188	}	188	}
189		189
190	static inline __address * get_ip()	190	static inline uintptr_t * get_ip()
191	{	191	{
192	__address *ip;	192	uintptr_t *ip;
193		193
194	__asm__ volatile (	194	__asm__ volatile (
195	"mov %%rip, %0"	195	"mov %%rip, %0"
196	: "=r" (ip)	196	: "=r" (ip)
197	);	197	);
Line 200...	Line 200...
200		200
201	/** Invalidate TLB Entry.	201	/** Invalidate TLB Entry.
202	*	202	*
203	* @param addr Address on a page whose TLB entry is to be invalidated.	203	* @param addr Address on a page whose TLB entry is to be invalidated.
204	*/	204	*/
205	static inline void invlpg(__address addr)	205	static inline void invlpg(uintptr_t addr)
206	{	206	{
207	__asm__ volatile ("invlpg %0\n" :: "m" (((__native )addr)));	207	__asm__ volatile ("invlpg %0\n" :: "m" (((unative_t )addr)));
208	}	208	}
209		209
210	/** Load GDTR register from memory.	210	/** Load GDTR register from memory.
211	*	211	*
212	* @param gdtr_reg Address of memory from where to load GDTR.	212	* @param gdtr_reg Address of memory from where to load GDTR.
Line 236...	Line 236...
236		236
237	/** Load TR from descriptor table.	237	/** Load TR from descriptor table.
238	*	238	*
239	* @param sel Selector specifying descriptor of TSS segment.	239	* @param sel Selector specifying descriptor of TSS segment.
240	*/	240	*/
241	static inline void tr_load(__u16 sel)	241	static inline void tr_load(uint16_t sel)
242	{	242	{
243	__asm__ volatile ("ltr %0" : : "r" (sel));	243	__asm__ volatile ("ltr %0" : : "r" (sel));
244	}	244	}
245		245
246	#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \	246	#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
247	{ \	247	{ \
248	__native res; \	248	unative_t res; \
249	__asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \	249	__asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
250	return res; \	250	return res; \
251	}	251	}
252		252
253	#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \	253	#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
254	{ \	254	{ \
255	__asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \	255	__asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
256	}	256	}
257		257
258	GEN_READ_REG(cr0);	258	GEN_READ_REG(cr0);

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(root)/kernel/trunk/arch/amd64/include/asm.h @ 1071 – Rev 1702 → 1780