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| 43 | speed of the decrementer or the counter register, respectively.</para> |
43 | speed of the decrementer or the counter register, respectively.</para> |
| 44 | 44 | ||
| 45 | <para>The rest of this section will, for the sake of clarity, focus on the |
45 | <para>The rest of this section will, for the sake of clarity, focus on the |
| 46 | two-register scheme. The decrementer scheme is very similar.</para> |
46 | two-register scheme. The decrementer scheme is very similar.</para> |
| 47 | 47 | ||
| 48 | <para>The kernel must reinitialize the counter registers after each clock |
48 | <para>The kernel must reinitialize one of the two registers after each |
| 49 | interrupt in order to schedule next interrupt. However this step is tricky |
49 | clock interrupt in order to schedule next interrupt. However this step is |
| 50 | and must be done with caution. Imagine that the clock interrupt is masked |
50 | tricky and must be done with caution. Imagine that the clock interrupt is |
| 51 | either because the kernel is servicing another interrupt or because the |
51 | masked either because the kernel is servicing another interrupt or because |
| 52 | processor locally disabled interrupts for a while. If the clock interrupt |
52 | the processor locally disabled interrupts for a while. If the clock |
| 53 | occurs during this period, it will be pending until interrupts are enabled |
53 | interrupt occurs during this period, it will be pending until interrupts |
| 54 | again. In theory, that could happen arbitrary counter register ticks |
54 | are enabled again. In theory, that could happen arbitrary counter register |
| 55 | later. Which is worse, the ideal time period between two non-delayed clock |
55 | ticks later. Which is worse, the ideal time period between two non-delayed |
| 56 | interrupts can also elapse arbitrary number of times before the delayed |
56 | clock interrupts can also elapse arbitrary number of times before the |
| 57 | interrupt gets serviced. The architecture-specific part of the clock |
57 | delayed interrupt gets serviced. The architecture-specific part of the |
| 58 | interrupt driver must avoid time drifts caused by this by taking proactive |
58 | clock interrupt driver must avoid time drifts caused by this by taking |
| 59 | counter-measures.</para> |
59 | proactive counter-measures.</para> |
| 60 | 60 | ||
| 61 | <para>Let us assume that the kernel wants each clock interrupt be |
61 | <para>Let us assume that the kernel wants each clock interrupt be |
| 62 | generated every <constant>TICKCONST</constant> ticks. This value |
62 | generated every <constant>TICKCONST</constant> ticks. This value |
| 63 | represents the ideal number of ticks between two non-delayed clock |
63 | represents the ideal number of ticks between two non-delayed clock |
| 64 | interrupts and has some known relation to real time. On each clock |
64 | interrupts and has some known relation to real time. On each clock |