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1 | <?xml version="1.0" encoding="UTF-8"?> |
1 | <?xml version="1.0" encoding="UTF-8"?> |
2 | 2 | ||
3 | <chapter id="architecture"><?dbhtml filename="arch.html"?> |
3 | <chapter id="architecture"><?dbhtml filename="arch.html"?> |
4 | <title>Architecture overview</title> |
4 | <title>Architecture overview</title> |
- | 5 | <section> |
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- | 6 | <title>Task</title> |
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- | 7 | <para>Task ID - unique 64 bit number. Used for syscalls.</para> |
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- | 8 | <para>Contains threads</para> |
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- | 9 | <para>Address space is created per task</para> |
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- | 10 | <para>Memory mapping is per task</para> |
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- | 11 | <para>Context per thread. (Note 2 stacks on IA64).</para> |
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5 | <para>Couple of words about microkernel concept etc </para> |
12 | <para>IPC answer box associated per task</para> |
- | 13 | </section> |
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- | 14 | <section> |
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- | 15 | <title>Memory management</title> |
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- | 16 | <para> |
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- | 17 | Zones - linked list (not many zones, so we can afford it. Can be replaced with B-tree in the future) |
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- | 18 | Number of zones depends on HW tables. Describe zone allocation/deallocation algoritm |
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- | 19 | </para> |
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- | 20 | <para>Page tables. 4 level hierarchical and hash directly supported. B+ Tree can be implemented. |
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- | 21 | <para>For paging there is an abstract layer</para> |
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- | 22 | <para>TLB shootdown implementation (update TLB upon mapping update/remove). |
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- | 23 | TLB shootdown ASID/ASID:PAGE/ALL. |
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- | 24 | TLB shootdown requests can come in asynchroniously |
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- | 25 | so there is a cache of TLB shootdown requests. Upon cache overflow TLB shootdown ALL is executed</para> |
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- | 26 | ||
- | 27 | <para> |
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- | 28 | Address spaces. Address space area (B+ tree). Only for uspace. Set of syscalls (shrink/extend etc). |
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- | 29 | Special address space area type - device - prohibits shrink/extend syscalls to call on it. |
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- | 30 | Address space has link to mapping tables (hierarchical - per Address space, hash - global tables). |
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- | 31 | </para> |
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6 | </chapter> |
32 | </chapter> |
7 | 33 |