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67 | expected to point just after the end of the thread local data. The |
67 | expected to point just after the end of the thread local data. The |
68 | application sometimes need to get a real address of the thread local |
68 | application sometimes need to get a real address of the thread local |
69 | data in its address space but it is impossible to read the base of the |
69 | data in its address space but it is impossible to read the base of the |
70 | FS segmentation register. The solution is to add the self-reference |
70 | FS segmentation register. The solution is to add the self-reference |
71 | address to the end of thread local data, so that the application can |
71 | address to the end of thread local data, so that the application can |
72 | read the address as %gs:0. </para> |
72 | read the address as %gs:0.</para> |
73 | 73 | ||
74 | <figure float="1"> |
74 | <figure float="1"> |
75 | <title>IA32 & AMD64</title> |
75 | <title>IA32 & AMD64</title> |
76 | 76 | ||
77 | <mediaobject id="tldia32"> |
77 | <mediaobject id="tldia32"> |
Line 165... | Line 165... | ||
165 | <imagedata fileref="images/tld_mips.svg" format="SVG" /> |
165 | <imagedata fileref="images/tld_mips.svg" format="SVG" /> |
166 | </imageobject> |
166 | </imageobject> |
167 | </mediaobject> |
167 | </mediaobject> |
168 | </figure> |
168 | </figure> |
169 | </section> |
169 | </section> |
- | 170 | ||
- | 171 | <section> |
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- | 172 | <title>Lazy FPU Context Switching</title> |
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- | 173 | ||
- | 174 | <para>Implementing lazy FPU switching on MIPS architecture is |
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- | 175 | straightforward. When coprocessor CP1 is disabled, any FPU intruction |
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- | 176 | raises a Coprocessor Unusable exception. The generic lazy FPU context |
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- | 177 | switch is then called that takes care of the correct context |
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- | 178 | save/restore.</para> |
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- | 179 | </section> |
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170 | </section> |
180 | </section> |
171 | 181 | ||
172 | <section> |
182 | <section> |
173 | <title>Power PC</title> |
183 | <title>Power PC</title> |
174 | 184 | ||
- | 185 | <para>PowerPC allows kernel to enable mode, where data and intruction |
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- | 186 | memory reads are not translated through virtual memory mapping |
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- | 187 | (<emphasis>real mode</emphasis>). The real mode is automatically enabled |
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- | 188 | when an exception occurs. However, the kernel uses the same memory |
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- | 189 | structure as on other 32-bit platforms - physical memory is mapped into |
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- | 190 | the top 2GB, userspace memory is available in the bottom half of the |
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- | 191 | 32-bit address space.</para> |
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- | 192 | ||
- | 193 | <section> |
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- | 194 | <title>OpenFirmware Boot</title> |
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- | 195 | ||
- | 196 | <para>The OpenFirmware loads an image of HelenOS operating system and |
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- | 197 | passes control to the HelenOS specific boot loader. The boot loader then |
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- | 198 | performs following tasks:</para> |
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- | 199 | ||
- | 200 | <itemizedlist> |
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- | 201 | <listitem> |
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- | 202 | <para>Fetches information from OpenFirmware regarding memory |
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- | 203 | structure, device information etc.</para> |
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- | 204 | </listitem> |
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- | 205 | ||
- | 206 | <listitem> |
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- | 207 | <para>Switches memory mapping to the real mode.</para> |
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- | 208 | </listitem> |
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- | 209 | ||
- | 210 | <listitem> |
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- | 211 | <para>Copies the kernel to proper physical address.</para> |
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- | 212 | </listitem> |
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- | 213 | ||
- | 214 | <listitem> |
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- | 215 | <para>Creates basic memory mapping and switches to the new kernel |
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- | 216 | mapping, in which the kernel can run.</para> |
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- | 217 | </listitem> |
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- | 218 | ||
- | 219 | <listitem> |
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- | 220 | <para>Passes control to the kernel <function>main_bsp</function> |
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- | 221 | function.</para> |
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- | 222 | </listitem> |
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- | 223 | </itemizedlist> |
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175 | <para></para> |
224 | </section> |
176 | 225 | ||
177 | <section> |
226 | <section> |
178 | <title>Thread Local Storage</title> |
227 | <title>Thread Local Storage</title> |
179 | 228 | ||
180 | <para>The Power PC thread local storage uses R2 register to hold an |
229 | <para>The Power PC thread local storage uses R2 register to hold an |
Line 182... | Line 231... | ||
182 | data. Overally it is the same as on the MIPS architecture.</para> |
231 | data. Overally it is the same as on the MIPS architecture.</para> |
183 | </section> |
232 | </section> |
184 | </section> |
233 | </section> |
185 | 234 | ||
186 | <section> |
235 | <section> |
187 | <title>IA-64</title> |
236 | <title>IA64</title> |
188 | 237 | ||
189 | <para></para> |
238 | <para></para> |
190 | 239 | ||
191 | <figure float="1"> |
240 | <section> |
192 | <title>IA64</title> |
241 | <title>Thread Local Storage</title> |
193 | 242 | ||
- | 243 | <para>Although thread local storage is not officially supported in |
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- | 244 | statically linked binaries, GCC supports it without any major obstacles. |
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- | 245 | As a thread pointer is designated register r13, the thread local data |
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- | 246 | section starts at an address r13+16.</para> |
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- | 247 | ||
- | 248 | <para><figure float="1"> |
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- | 249 | <title>IA64</title> |
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- | 250 | ||
194 | <mediaobject id="tldia64"> |
251 | <mediaobject id="tldia64"> |
195 | <imageobject role="pdf"> |
252 | <imageobject role="pdf"> |
196 | <imagedata fileref="images/tld_ia64.pdf" format="PDF" /> |
253 | <imagedata fileref="images/tld_ia64.pdf" format="PDF" /> |
197 | </imageobject> |
254 | </imageobject> |
198 | 255 | ||
199 | <imageobject role="html"> |
256 | <imageobject role="html"> |
200 | <imagedata fileref="images/tld_ia64.png" format="PNG" /> |
257 | <imagedata fileref="images/tld_ia64.png" format="PNG" /> |
201 | </imageobject> |
258 | </imageobject> |
202 | 259 | ||
203 | <imageobject role="fop"> |
260 | <imageobject role="fop"> |
204 | <imagedata fileref="images/tld_ia64.svg" format="SVG" /> |
261 | <imagedata fileref="images/tld_ia64.svg" format="SVG" /> |
205 | </imageobject> |
262 | </imageobject> |
206 | </mediaobject> |
263 | </mediaobject> |
- | 264 | </figure></para> |
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207 | </figure> |
265 | </section> |
208 | </section> |
266 | </section> |
209 | </appendix> |
267 | </appendix> |
210 | 268 |