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Rev 3597 Rev 4377
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup ia64mm 
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/** @addtogroup ia64mm
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 */
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 */
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/** Initialize VHPT and region registers. */
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/** Initialize VHPT and region registers. */
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void set_environment(void)
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void set_environment(void)
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{
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{
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    region_register rr;
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    region_register rr;
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    pta_register pta;  
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    pta_register pta;
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    int i;
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    int i;
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#ifdef CONFIG_VHPT 
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#ifdef CONFIG_VHPT
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    uintptr_t vhpt_base;
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    uintptr_t vhpt_base;
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#endif
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#endif
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    /*
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    /*
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     * First set up kernel region register.
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     * First set up kernel region register.
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/** Calculate address of collision chain from VPN and ASID.
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/** Calculate address of collision chain from VPN and ASID.
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 *
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 *
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 * Interrupts must be disabled.
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 * Interrupts must be disabled.
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 *
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 *
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 * @param page Address of virtual page including VRN bits.
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 * @param page      Address of virtual page including VRN bits.
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 * @param asid Address space identifier.
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 * @param asid      Address space identifier.
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 *
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 *
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 * @return VHPT entry address.
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 * @return      VHPT entry address.
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 */
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 */
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vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid)
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vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid)
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{
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{
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    region_register rr_save, rr;
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    region_register rr_save, rr;
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    index_t vrn;
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    index_t vrn;
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/** Compare ASID and VPN against PTE.
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/** Compare ASID and VPN against PTE.
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 *
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 *
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 * Interrupts must be disabled.
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 * Interrupts must be disabled.
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 *
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 *
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 * @param page Address of virtual page including VRN bits.
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 * @param page      Address of virtual page including VRN bits.
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 * @param asid Address space identifier.
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 * @param asid      Address space identifier.
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 *
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 *
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 * @return True if page and asid match the page and asid of t, false otherwise.
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 * @return      True if page and asid match the page and asid of t,
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 *          false otherwise.
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 */
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 */
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bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v)
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bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v)
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{
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{
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    region_register rr_save, rr;   
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    region_register rr_save, rr;   
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    index_t vrn;
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    index_t vrn;
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}
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}
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/** Set up one VHPT entry.
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/** Set up one VHPT entry.
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 *
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 *
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 * @param v VHPT entry to be set up.
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 * @param v VHPT entry to be set up.
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 * @param page Virtual address of the page mapped by the entry.
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 * @param page      Virtual address of the page mapped by the entry.
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 * @param asid Address space identifier of the address space to which page belongs.
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 * @param asid      Address space identifier of the address space to which
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 *          page belongs.
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 * @param frame Physical address of the frame to wich page is mapped.
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 * @param frame     Physical address of the frame to wich page is mapped.
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 * @param flags Different flags for the mapping.
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 * @param flags     Different flags for the mapping.
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 */
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 */
- 
 
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void
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void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags)
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vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame,
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    int flags)
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{
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{
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    region_register rr_save, rr;   
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    region_register rr_save, rr;   
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    index_t vrn;
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    index_t vrn;
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    rid_t rid;
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    rid_t rid;
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    uint64_t tag;
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    uint64_t tag;
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    v->word[1] = 0;
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    v->word[1] = 0;
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    v->word[2] = 0;
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    v->word[2] = 0;
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    v->word[3] = 0;
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    v->word[3] = 0;
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    v->present.p = true;
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    v->present.p = true;
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    v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
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    v->present.ma = (flags & PAGE_CACHEABLE) ?
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        MA_WRITEBACK : MA_UNCACHEABLE;
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    v->present.a = false;   /* not accessed */
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    v->present.a = false;   /* not accessed */
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    v->present.d = false;   /* not dirty */
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    v->present.d = false;   /* not dirty */
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    v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
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    v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
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    v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
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    v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
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    v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
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    v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
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    v->present.ps = PAGE_WIDTH;
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    v->present.ps = PAGE_WIDTH;
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    v->present.key = 0;
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    v->present.key = 0;
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    v->present.tag.tag_word = tag;
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    v->present.tag.tag_word = tag;
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}
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}
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extern uintptr_t last_frame;
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uintptr_t hw_map(uintptr_t physaddr, size_t size)
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uintptr_t hw_map(uintptr_t physaddr, size_t size __attribute__ ((unused)))
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{
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{
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    if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
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        panic("Unable to map physical memory %p (%d bytes)", physaddr, size)
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    uintptr_t virtaddr = PA2KA(last_frame);
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    pfn_t i;
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    for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++) {
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        uintptr_t addr = PFN2ADDR(i);
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    /* THIS is a dirty hack. */
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        page_mapping_insert(AS_KERNEL, virtaddr + addr, physaddr + addr, PAGE_NOT_CACHEABLE | PAGE_WRITE);
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    }
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    last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE);
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    return (uintptr_t)((uint64_t)(PA2KA(physaddr)) + VIO_OFFSET);
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    return virtaddr;
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}
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}
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 - 
 
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/** @}
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/** @}
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 */
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 */