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Rev 3424 Rev 4377
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 24 
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 25 
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 26 
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
 27 
 */
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 28 
 
29 
/** @addtogroup ia32   
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/** @addtogroup ia32
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 */
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 */
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 34 
 
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    d->offset_16_31 = offset >> 16;
 110 
    d->offset_16_31 = offset >> 16;
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}
 111 
}
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 112 
 
113 
void tss_initialize(tss_t *t)
 113 
void tss_initialize(tss_t *t)
114 
{
 114 
{
115 
    memsetb(t, sizeof(struct tss), 0);
 115 
    memsetb(t, sizeof(tss_t), 0);
116 
}
 116 
}
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 117 
 
118 
/*
 118 
/*
119 
 * This function takes care of proper setup of IDT and IDTR.
 119 
 * This function takes care of proper setup of IDT and IDTR.
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 */
 120 
 */
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 125 
 
126 
    for (i = 0; i < IDT_ITEMS; i++) {
 126 
    for (i = 0; i < IDT_ITEMS; i++) {
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        d = &idt[i];
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        d = &idt[i];
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 128 
 
129 
        d->unused = 0;
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        d->unused = 0;
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        d->selector = selector(KTEXT_DES);
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        d->selector = gdtselector(KTEXT_DES);
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 131 
 
132 
        d->access = AR_PRESENT | AR_INTERRUPT;  /* masking interrupt */
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        d->access = AR_PRESENT | AR_INTERRUPT;  /* masking interrupt */
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 133 
 
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        if (i == VECTOR_SYSCALL || i == VECTOR_BREAKPOINT) {
 134 
        if (i == VECTOR_SYSCALL || i == VECTOR_BREAKPOINT) {
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            /*
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            /*
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        "pushfl\n"
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        "pushfl\n"
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        "pop %%eax\n"
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        "pop %%eax\n"
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        "and $0xffff8fff, %%eax\n"
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        "and $0xffff8fff, %%eax\n"
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        "push %%eax\n"
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        "push %%eax\n"
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        "popfl\n"
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        "popfl\n"
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        : : : "eax"
 157 
        ::: "eax"
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    );
 158 
    );
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}
 159 
}
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 160 
 
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/* Clean AM(18) flag in CR0 register */
 161 
/* Clean AM(18) flag in CR0 register */
162 
static void clean_AM_flag(void)
 162 
static void clean_AM_flag(void)
163 
{
 163 
{
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    asm volatile (
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    asm volatile (
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        "mov %%cr0, %%eax\n"
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        "mov %%cr0, %%eax\n"
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        "and $0xfffbffff, %%eax\n"
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        "and $0xfffbffff, %%eax\n"
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        "mov %%eax, %%cr0\n"
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        "mov %%eax, %%cr0\n"
168 
        : : : "eax"
 168 
        ::: "eax"
169 
    );
 169 
    );
170 
}
 170 
}
171 
 
 171 
 
172 
void pm_init(void)
 172 
void pm_init(void)
173 
{
 173 
{
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        tss_p = &tss;
 196 
        tss_p = &tss;
197 
    }
 197 
    }
198 
    else {
 198 
    else {
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        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
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        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
200 
        if (!tss_p)
 200 
        if (!tss_p)
201 
            panic("could not allocate TSS\n");
 201 
            panic("Cannot allocate TSS.");
202 
    }
 202 
    }
203 
 
 203 
 
204 
    tss_initialize(tss_p);
 204 
    tss_initialize(tss_p);
205 
   
 205 
   
206 
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
 206 
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
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 212 
 
213 
    /*
 213 
    /*
214 
     * As of this moment, the current CPU has its own GDT pointing
 214 
     * As of this moment, the current CPU has its own GDT pointing
215 
     * to its own TSS. We just need to load the TR register.
 215 
     * to its own TSS. We just need to load the TR register.
216 
     */
 216 
     */
217 
    tr_load(selector(TSS_DES));
 217 
    tr_load(gdtselector(TSS_DES));
218 
   
 218 
   
219 
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
 219 
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
220 
    clean_AM_flag();          /* Disable alignment check */
 220 
    clean_AM_flag();          /* Disable alignment check */
221 
}
 221 
}
222 
 
 222 
 
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    gdt_setbase(&gdt_p[TLS_DES], tls);
 230 
    gdt_setbase(&gdt_p[TLS_DES], tls);
231 
    /* Reload gdt register to update GS in CPU */
 231 
    /* Reload gdt register to update GS in CPU */
232 
    gdtr_load(&cpugdtr);
 232 
    gdtr_load(&cpugdtr);
233 
}
 233 
}
234 
 
 234 
 
235 
/* Reboot the machine by initiating
 - 
 
236 
 * a triple fault
 - 
 
237 
 */
 - 
 
238 
void arch_reboot(void)
 - 
 
239 
{
 - 
 
240 
    preemption_disable();
 - 
 
241 
    ipl_t ipl = interrupts_disable();
 - 
 
242 
   
 - 
 
243 
    memsetb(idt, sizeof(idt), 0);
 - 
 
244 
   
 - 
 
245 
    ptr_16_32_t idtr;
 - 
 
246 
    idtr.limit = sizeof(idt);
 - 
 
247 
    idtr.base = (uintptr_t) idt;
 - 
 
248 
    idtr_load(&idtr);
 - 
 
249 
   
 - 
 
250 
    interrupts_restore(ipl);
 - 
 
251 
    asm volatile (
 - 
 
252 
        "int $0x03\n"
 - 
 
253 
        "cli\n"
 - 
 
254 
        "hlt\n"
 - 
 
255 
    );
 - 
 
256 
}
 - 
 
257 
 
 - 
 
258 
/** @}
 235 
/** @}
259 
 */
 236 
 */