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Line 447... Line 447...
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/*
 449 
/*
450 
 * Spills the window at CWP + 2 to the kernel stack. This macro is to be
 450 
 * Spills the window at CWP + 2 to the kernel stack. This macro is to be
451 
 * used before doing SAVE when the spill trap is undesirable.
 451 
 * used before doing SAVE when the spill trap is undesirable.
- 
 
 452 
 *
- 
 
 453 
 * Parameters:
- 
 
 454 
 * 	tmpreg1		global register to be used for scratching purposes
- 
 
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 * 	tmpreg2		global register to be used for scratching purposes
452 
 */
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 */
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.macro INLINE_SPILL
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.macro INLINE_SPILL tmpreg1, tmpreg2
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	! CWP := CWP + 2
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	! CWP := CWP + 2
455 
	rdpr %cwp, %g3
 459 
	rdpr %cwp, \tmpreg2
456 
	add %g3, 2, %g3
 460 
	add \tmpreg2, 2, \tmpreg1
457 
	and %g3, NWINDOWS - 1, %g3		! modulo NWINDOWS
 461 
	and \tmpreg1, NWINDOWS - 1, \tmpreg1		! modulo NWINDOWS
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	wrpr %g3, %cwp
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	wrpr \tmpreg1, %cwp
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463
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	! spill to kernel stack
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	! spill to kernel stack
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	stx %l0, [%sp + STACK_BIAS + L0_OFFSET]
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	stx %l0, [%sp + STACK_BIAS + L0_OFFSET]
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	stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
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	stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
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	stx %l2, [%sp + STACK_BIAS + L2_OFFSET]
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	stx %l2, [%sp + STACK_BIAS + L2_OFFSET]
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	stx %i5, [%sp + STACK_BIAS + I5_OFFSET]
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	stx %i5, [%sp + STACK_BIAS + I5_OFFSET]
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	stx %i6, [%sp + STACK_BIAS + I6_OFFSET]
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	stx %i6, [%sp + STACK_BIAS + I6_OFFSET]
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	stx %i7, [%sp + STACK_BIAS + I7_OFFSET]
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	stx %i7, [%sp + STACK_BIAS + I7_OFFSET]
477 
 
 481 
 
478 
	! CWP := CWP - 2
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	! CWP := CWP - 2
479 
	add %g3, NWINDOWS - 2, %g3
 - 
 
480 
	and %g3, NWINDOWS - 1, %g3		! modulo NWINDOWS
 - 
 
481 
	wrpr %g3, %cwp
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	wrpr \tmpreg2, %cwp
482 
 
 484 
 
483 
	saved
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	saved
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.endm
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.endm
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 487 
 
486 
/*
 488 
/*
487 
 * Fill the window at CWP - 1 from the kernel stack. This macro is to be
 489 
 * Fill the window at CWP - 1 from the kernel stack. This macro is to be
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 * used before doing RESTORE when the fill trap is undesirable.
 490 
 * used before doing RESTORE when the fill trap is undesirable.
- 
 
 491 
 *
- 
 
 492 
 * Parameters:
- 
 
 493 
 * 	tmpreg1		global register to be used for scratching purposes
- 
 
 494 
 * 	tmpreg2		global register to be used for scratching purposes
489 
 */
 495 
 */
490 
.macro INLINE_FILL
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.macro INLINE_FILL tmpreg1, tmpreg2
491 
	! CWP := CWP - 1
 497 
	! CWP := CWP - 1
492 
	rdpr %cwp, %g3
 498 
	rdpr %cwp, \tmpreg2
493 
	add %g3, NWINDOWS - 1, %g3
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	add \tmpreg2, NWINDOWS - 1, \tmpreg1
494 
	and %g3, NWINDOWS - 1, %g3
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	and \tmpreg1, NWINDOWS - 1, \tmpreg1
495 
	wrpr %g3, %cwp
 501 
	wrpr \tmpreg1, %cwp
496 
 
 502 
 
497 
	! fill
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	! fill from kernel stack
498 
	ldx [%sp + STACK_BIAS + L0_OFFSET], %l0
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	ldx [%sp + STACK_BIAS + L0_OFFSET], %l0
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	ldx [%sp + STACK_BIAS + L1_OFFSET], %l1
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	ldx [%sp + STACK_BIAS + L1_OFFSET], %l1
500 
	ldx [%sp + STACK_BIAS + L2_OFFSET], %l2
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	ldx [%sp + STACK_BIAS + L2_OFFSET], %l2
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	ldx [%sp + STACK_BIAS + L3_OFFSET], %l3
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	ldx [%sp + STACK_BIAS + L3_OFFSET], %l3
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	ldx [%sp + STACK_BIAS + L4_OFFSET], %l4
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	ldx [%sp + STACK_BIAS + L4_OFFSET], %l4
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	ldx [%sp + STACK_BIAS + I5_OFFSET], %i5
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	ldx [%sp + STACK_BIAS + I5_OFFSET], %i5
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	ldx [%sp + STACK_BIAS + I6_OFFSET], %i6
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	ldx [%sp + STACK_BIAS + I6_OFFSET], %i6
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	ldx [%sp + STACK_BIAS + I7_OFFSET], %i7
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	ldx [%sp + STACK_BIAS + I7_OFFSET], %i7
514 
 
 520 
 
515 
	! CWP := CWP + 1
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	! CWP := CWP + 1
516 
	add %g3, 1, %g3
 - 
 
517 
	and %g3, NWINDOWS - 1, %g3
 - 
 
518 
	wrpr %g3, %cwp
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	wrpr \tmpreg2, %cwp
519 
 
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520 
	restored
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	restored
521 
.endm
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.endm
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 526 
 
523 
/*
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/*
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	/* prevent unnecessary CLEANWIN exceptions */
 542 
	/* prevent unnecessary CLEANWIN exceptions */
539 
	wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate
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	wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate
540 
1:
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1:
541 
	/*
 545 
	/*
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	 * Prevent SAVE instruction from causing a spill exception. If the
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	 * Prevent SAVE instruction from causing a spill exception. If the
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	 * CANSAVE register is zero, explicitly spill the current register
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	 * CANSAVE register is zero, explicitly spill register window
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	 * window.
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	 * at CWP + 2.
545 
	 */
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	 */
546 
 
 550 
 
547 
	rdpr %cansave, %g3
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	rdpr %cansave, %g3
548 
	brnz %g3, 2f
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	brnz %g3, 2f
549 
	nop
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	nop
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	INLINE_SPILL
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	INLINE_SPILL %g3, %g4
551 
 
 555 
 
552 
2:
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2:
553 
	/* ask for new register window */
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	/* ask for new register window */
554 
	save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
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	save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
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578 
	rd %y, %g4
 582 
	rd %y, %g4
579 
	stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y]
 583 
	stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y]
580 
 
 584 
 
581 
	/* switch to TL = 0, explicitly enable FPU */
 585 
	/* switch to TL = 0, explicitly enable FPU */
582 
	wrpr %g0, 0, %tl
 586 
	wrpr %g0, 0, %tl
- 
 
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	wrpr %g0, 0, %gl
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	wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate
 588 
	wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate
584 
 
 589 
 
585 
	/* g1 -> l1, ..., g7 -> l7 */
 590 
	/* g1 -> l1, ..., g7 -> l7 */
586 
	SAVE_GLOBALS
 591 
	SAVE_GLOBALS
587 
 
 592 
 
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	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6
 664 
	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6
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	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7
 665 
	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7
661 
 
 666 
 
662 
4:
 667 
4:
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	/*
 668 
	/*
664 
	 * Prevent RESTORE instruction from causing a spill exception. If the
 669 
	 * Prevent RESTORE instruction from causing a fill exception. If the
665 
	 * CANRESTORE register is zero, explicitly spill the current register
 670 
	 * CANRESTORE register is zero, explicitly fill register window
666 
	 * window.
 671 
	 * at CWP - 1.
667 
	 */
 672 
	 */
668 
	rdpr %canrestore, %g1
 673 
	rdpr %canrestore, %g1
669 
	brnz %g1, 5f
 674 
	brnz %g1, 5f
670 
	nop
 675 
	nop
671 
	INLINE_FILL
 676 
	INLINE_FILL %g3, %g4
672 
 
 677 
 
673 
5:
 678 
5:
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	restore
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	restore
675 
 
 680 
 
676 
	retry
 681 
	retry