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Rev 4129 Rev 4433
Line 69... Line 69...
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        cnt = TSB_ENTRY_COUNT;
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        cnt = TSB_ENTRY_COUNT;
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    else
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    else
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        cnt = pages;
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        cnt = pages;
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    for (i = 0; i < cnt; i++) {
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    for (i = 0; i < cnt; i++) {
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        ((tsb_entry_t *) as->arch.tsb_description.tsb_base)[
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        ((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[
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            (i0 + i) & (TSB_ENTRY_COUNT - 1)].data.v = false;
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            (i0 + i) & (TSB_ENTRY_COUNT - 1)].data.v = false;
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    }
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    }
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}
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}
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/** Copy software PTE to ITSB.
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/** Copy software PTE to ITSB.
Line 87... Line 87...
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    index_t entry;
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    index_t entry;
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 88 
 
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    as = t->as;
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    as = t->as;
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    entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
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    entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
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    ASSERT(entry < TSB_ENTRY_COUNT);
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    ASSERT(entry < TSB_ENTRY_COUNT);
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    tsb = &((tsb_entry_t *) as->arch.tsb_description.tsb_base)[entry];
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    tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry];
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    /*
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    /*
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     * We use write barriers to make sure that the TSB load
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     * We use write barriers to make sure that the TSB load
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     * won't use inconsistent data or that the fault will
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     * won't use inconsistent data or that the fault will
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     * be repeated.
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     * be repeated.
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    tsb->data.v = false;
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    tsb->data.v = false;
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    write_barrier();
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    write_barrier();
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    tsb->tag.context = as->asid;
 - 
 
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    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
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    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
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    tsb->data.value = 0;
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    tsb->data.value = 0;
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    tsb->data.nfo = false;
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    tsb->data.nfo = false;
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    tsb->data.ra = t->frame >> MMU_FRAME_WIDTH;
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    tsb->data.ra = t->frame >> MMU_FRAME_WIDTH;
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    index_t entry;
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    index_t entry;
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 133 
 
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    as = t->as;
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    as = t->as;
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    entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
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    entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
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    ASSERT(entry < TSB_ENTRY_COUNT);
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    ASSERT(entry < TSB_ENTRY_COUNT);
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    tsb = &((tsb_entry_t *) as->arch.tsb_description.tsb_base)[entry];
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    tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry];
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 138 
 
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    /*
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    /*
141 
     * We use write barriers to make sure that the TSB load
 140 
     * We use write barriers to make sure that the TSB load
142 
     * won't use inconsistent data or that the fault will
 141 
     * won't use inconsistent data or that the fault will
143 
     * be repeated.
 142 
     * be repeated.
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 144 
 
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    tsb->data.v = false;
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    tsb->data.v = false;
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 146 
 
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    write_barrier();
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    write_barrier();
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 148 
 
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    tsb->tag.context = as->asid;
 - 
 
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    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
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    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
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 150 
 
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    tsb->data.value = 0;
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    tsb->data.value = 0;
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    tsb->data.nfo = false;
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    tsb->data.nfo = false;
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    tsb->data.ra = t->frame >> MMU_FRAME_WIDTH;
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    tsb->data.ra = t->frame >> MMU_FRAME_WIDTH;