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         * TSBs were allocated from memory not covered
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         * TSBs were allocated from memory not covered
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         * by the locked 4M kernel DTLB entry. We need
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         * by the locked 4M kernel DTLB entry. We need
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         * to map both TSBs explicitly.
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         * to map both TSBs explicitly.
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         */
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         */
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        mmu_demap_page(tsb, 0, MMU_FLAG_DTLB);
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        mmu_demap_page(tsb, 0, MMU_FLAG_DTLB);
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        mmu_map_perm_addr(
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            tsb, KA2PA(tsb), true, true, false, true,
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        dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
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            PAGESIZE_64K, MMU_FLAG_DTLB);
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    }
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    }
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    __hypercall_fast2(MMU_TSB_CTX0, 1, as->arch.tsb_description.tsb_base);
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    __hypercall_fast2(MMU_TSB_CTX0, 1, as->arch.tsb_description.tsb_base);
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#endif
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#endif
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        /*
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        /*
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         * TSBs were allocated from memory not covered
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         * TSBs were allocated from memory not covered
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         * by the locked 4M kernel DTLB entry. We need
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         * by the locked 4M kernel DTLB entry. We need
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         * to demap the entry installed by as_install_arch().
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         * to demap the entry installed by as_install_arch().
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         */
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         */
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        mmu_demap_page(tsb, 0, MMU_FLAG_DTLB);
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        __hypercall_fast3(MMU_UNMAP_PERM_ADDR, tsb, 0, MMU_FLAG_DTLB);
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    }
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    }
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#endif
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#endif
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}
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}
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/** @}
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/** @}