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/** @addtogroup sparc64interrupt
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/** @addtogroup sparc64interrupt
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 * @{
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 * @{
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 */
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 */
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/**
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/**
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 * @file
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 * @file
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 * @brief This file contains interrupt vector trap handler.
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 * @brief This file contains level N interrupt and inter-processor interrupt
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 * trap handler.
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 */
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 */
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#ifndef KERN_sparc64_TRAP_INTERRUPT_H_
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#ifndef KERN_sparc64_INTERRUPT_TRAP_H_
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#define KERN_sparc64_TRAP_INTERRUPT_H_
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#define KERN_sparc64_INTERRUPT_TRAP_H_
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#include <arch/trap/trap_table.h>
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#include <arch/stack.h>
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/* IMAP register bits */
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#define IGN_MASK    0x7c0
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#define INO_MASK    0x1f
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#define IMAP_V_MASK (1ULL << 31)
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#define IGN_SHIFT   6
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/* Interrupt ASI registers. */
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#define ASI_INTR_W          0x77
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#define ASI_INTR_DISPATCH_STATUS    0x48
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#define ASI_INTR_R          0x7f
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#define ASI_INTR_RECEIVE        0x49
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/* VA's used with ASI_INTR_W register. */
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#if defined (US)
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#define ASI_UDB_INTR_W_DATA_0   0x40
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#define ASI_UDB_INTR_W_DATA_1   0x50
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#define ASI_UDB_INTR_W_DATA_2   0x60
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#elif defined (US3)
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#define VA_INTR_W_DATA_0    0x40
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#define VA_INTR_W_DATA_1    0x48
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#define VA_INTR_W_DATA_2    0x50
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#define VA_INTR_W_DATA_3    0x58
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#define VA_INTR_W_DATA_4    0x60
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#define VA_INTR_W_DATA_5    0x68
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#define VA_INTR_W_DATA_6    0x80
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#define VA_INTR_W_DATA_7    0x88
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#endif
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#define VA_INTR_W_DISPATCH  0x70
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/* VA's used with ASI_INTR_R register. */
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#if defined(US)
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#define ASI_UDB_INTR_R_DATA_0   0x40
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#define ASI_UDB_INTR_R_DATA_1   0x50
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#define ASI_UDB_INTR_R_DATA_2   0x60
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#elif defined (US3)
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#define VA_INTR_R_DATA_0    0x40
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#define VA_INTR_R_DATA_1    0x48
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#define VA_INTR_R_DATA_2    0x50
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#define VA_INTR_R_DATA_3    0x58
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#define VA_INTR_R_DATA_4    0x60
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#define VA_INTR_R_DATA_5    0x68
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#define VA_INTR_R_DATA_6    0x80
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#define VA_INTR_R_DATA_7    0x88
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#endif
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/* Shifts in the Interrupt Vector Dispatch virtual address. */
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#define INTR_VEC_DISPATCH_MID_SHIFT 14
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/* Bits in the Interrupt Dispatch Status register. */
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#define INTR_DISPATCH_STATUS_NACK   0x2
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#define INTR_DISPATCH_STATUS_BUSY   0x1
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#define TT_INTERRUPT_LEVEL_1            0x41
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#define TT_INTERRUPT_LEVEL_1            0x41
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#define TT_INTERRUPT_LEVEL_2            0x42
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#define TT_INTERRUPT_LEVEL_2            0x42
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#define TT_INTERRUPT_LEVEL_3            0x43
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#define TT_INTERRUPT_LEVEL_3            0x43
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#define TT_INTERRUPT_LEVEL_4            0x44
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#define TT_INTERRUPT_LEVEL_4            0x44
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#define TT_INTERRUPT_LEVEL_12           0x4c
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#define TT_INTERRUPT_LEVEL_12           0x4c
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#define TT_INTERRUPT_LEVEL_13           0x4d
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#define TT_INTERRUPT_LEVEL_13           0x4d
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#define TT_INTERRUPT_LEVEL_14           0x4e
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#define TT_INTERRUPT_LEVEL_14           0x4e
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#define TT_INTERRUPT_LEVEL_15           0x4f
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#define TT_INTERRUPT_LEVEL_15           0x4f
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#define TT_INTERRUPT_VECTOR_TRAP        0x60
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#define INTERRUPT_LEVEL_N_HANDLER_SIZE      TRAP_TABLE_ENTRY_SIZE
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#define INTERRUPT_LEVEL_N_HANDLER_SIZE      TRAP_TABLE_ENTRY_SIZE
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/* IMAP register bits */
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#define IGN_MASK    0x7c0
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#define INO_MASK    0x1f
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#define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE  TRAP_TABLE_ENTRY_SIZE
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#define IMAP_V_MASK (1ULL << 31)
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#define IGN_SHIFT   6
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#ifdef __ASM__
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#ifdef __ASM__
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.macro INTERRUPT_LEVEL_N_HANDLER n
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.macro INTERRUPT_LEVEL_N_HANDLER n
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    mov \n - 1, %g2
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    mov \n - 1, %g2
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    PREEMPTIBLE_HANDLER exc_dispatch
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    PREEMPTIBLE_HANDLER exc_dispatch
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.endm
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.endm
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.macro INTERRUPT_VECTOR_TRAP_HANDLER
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    PREEMPTIBLE_HANDLER interrupt
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.endm
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#endif
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#endif /* __ASM__ */
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#ifndef __ASM__
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#ifndef __ASM__
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#include <arch/interrupt.h>
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#include <arch/interrupt.h>
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extern void interrupt(int n, istate_t *istate);
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extern void interrupt(int n, istate_t *istate);
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#endif /* !def __ASM__ */
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#endif /* !def __ASM__ */
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#if defined (SUN4U)
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#include <arch/trap/sun4u/interrupt.h>
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#elif defined (SUN4V)
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#include <arch/trap/sun4v/interrupt.h>
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#endif
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#endif
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#endif
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/** @}
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/** @}
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 */
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 */