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Line 52... | Line 52... | ||
52 | #define ASI_INTR_W 0x77 |
52 | #define ASI_INTR_W 0x77 |
53 | #define ASI_INTR_DISPATCH_STATUS 0x48 |
53 | #define ASI_INTR_DISPATCH_STATUS 0x48 |
54 | #define ASI_INTR_R 0x7f |
54 | #define ASI_INTR_R 0x7f |
55 | #define ASI_INTR_RECEIVE 0x49 |
55 | #define ASI_INTR_RECEIVE 0x49 |
56 | 56 | ||
57 | /* VA's used with ASI_UDB_INTR_W register. */ |
57 | /* VA's used with ASI_INTR_W register. */ |
58 | #if defined (US) |
58 | #if defined (US) |
59 | #define ASI_UDB_INTR_W_DATA_0 0x40 |
59 | #define ASI_UDB_INTR_W_DATA_0 0x40 |
60 | #define ASI_UDB_INTR_W_DATA_1 0x50 |
60 | #define ASI_UDB_INTR_W_DATA_1 0x50 |
61 | #define ASI_UDB_INTR_W_DATA_2 0x60 |
61 | #define ASI_UDB_INTR_W_DATA_2 0x60 |
62 | #elif defined (US3) |
62 | #elif defined (US3) |
Line 69... | Line 69... | ||
69 | #define VA_INTR_W_DATA_6 0x80 |
69 | #define VA_INTR_W_DATA_6 0x80 |
70 | #define VA_INTR_W_DATA_7 0x88 |
70 | #define VA_INTR_W_DATA_7 0x88 |
71 | #endif |
71 | #endif |
72 | #define VA_INTR_W_DISPATCH 0x70 |
72 | #define VA_INTR_W_DISPATCH 0x70 |
73 | 73 | ||
74 | /* VA's used with ASI_UDB_INTR_R register. */ |
74 | /* VA's used with ASI_INTR_R register. */ |
75 | #if defined(US) |
75 | #if defined(US) |
76 | #define ASI_UDB_INTR_R_DATA_0 0x40 |
76 | #define ASI_UDB_INTR_R_DATA_0 0x40 |
77 | #define ASI_UDB_INTR_R_DATA_1 0x50 |
77 | #define ASI_UDB_INTR_R_DATA_1 0x50 |
78 | #define ASI_UDB_INTR_R_DATA_2 0x60 |
78 | #define ASI_UDB_INTR_R_DATA_2 0x60 |
79 | #elif defined (US3) |
79 | #elif defined (US3) |