WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/include/mm/sun4u/tlb.h



/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
#if defined (US3)
#define DTLB_MAX_LOCKED_ENTRIES     16
#endif
 
#define MEM_CONTEXT_KERNEL      0
#define MEM_CONTEXT_TEMP        1
 
/** Bit width of the TLB-locked portion of kernel address space. */
#define KERNEL_PAGE_WIDTH       22  /* 4M */
 
/* TLB Demap Operation types. */
#define TLB_DEMAP_PAGE      0

#include <arch/mm/page.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/types.h>
#include <arch/register.h>
#include <arch/sun4u/cpu.h>
 
union tlb_context_reg {
    uint64_t v;
    struct {
        unsigned long : 51;

 
/*
 * In US3, I-MMU and D-MMU have different formats of the data
 * access register virtual address. In the corresponding
 * structures the member variable for the entry number is
 * called "local_tlb_entry" - it contrasts with the "tlb_entry"
 * for the US data access register VA structure. The rationale
 * behind this is to prevent careless mistakes in the code
 * caused by setting only the entry number and not the TLB
 * number in the US3 code (when taking the code from US).
 */

 * Functions for determining the number of entries in TLBs. They either return
 * a constant value or a value based on the CPU autodetection.
 */
 
/**
 * Determine the number of entries in the DMMU's small TLB.
 */
static inline uint16_t tlb_dsmall_size(void)
{
    return 16;
}
 
/**
 * Determine the number of entries in each DMMU's big TLB.
 */
static inline uint16_t tlb_dbig_size(void)
{
    return 512;
}
 
/**
 * Determine the number of entries in the IMMU's small TLB.
 */
static inline uint16_t tlb_ismall_size(void)
{
    return 16;
}
 
/**
 * Determine the number of entries in the IMMU's big TLB.
 */
static inline uint16_t tlb_ibig_size(void)
{
    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
        return 512;

 
#endif
 
/** Read MMU Primary Context Register.
 *
 * @return      Current value of Primary Context Register.
 */
static inline uint64_t mmu_primary_context_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
 *
 * @param v     New value of Primary Context Register.
 */
static inline void mmu_primary_context_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
    flush_pipeline();
}
 
/** Read MMU Secondary Context Register.
 *
 * @return      Current value of Secondary Context Register.
 */
static inline uint64_t mmu_secondary_context_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
 *
 * @param v     New value of Primary Context Register.
 */
static inline void mmu_secondary_context_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
    flush_pipeline();

 
#if defined (US)
 
/** Read IMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Data Access
 *          Register.
 */
static inline uint64_t itlb_data_access_read(index_t entry)
{
    itlb_data_access_addr_t reg;
   

    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void itlb_data_access_write(index_t entry, uint64_t value)
{
    itlb_data_access_addr_t reg;
   

    flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Data Access
 *          Register.
 */
static inline uint64_t dtlb_data_access_read(index_t entry)
{
    dtlb_data_access_addr_t reg;
   

    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
 *
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void dtlb_data_access_write(index_t entry, uint64_t value)
{
    dtlb_data_access_addr_t reg;
   

    membar();
}
 
/** Read IMMU TLB Tag Read Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(index_t entry)
{
    itlb_tag_read_addr_t tag;
 

    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
 *
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(index_t entry)
{
    dtlb_tag_read_addr_t tag;
 

#elif defined (US3)
 
 
/** Read IMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Data Access
 *          Register.
 */
static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
{
    itlb_data_access_addr_t reg;
   

    reg.local_tlb_entry = entry;
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void itlb_data_access_write(int tlb, index_t entry,
    uint64_t value)
{
    itlb_data_access_addr_t reg;

    flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Data Access
 *          Register.
 */
static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
{
    dtlb_data_access_addr_t reg;
   

    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)  
 * @param entry     TLB Entry index.
 * @param value     Value to be written.
 */
static inline void dtlb_data_access_write(int tlb, index_t entry,
    uint64_t value)
{
    dtlb_data_access_addr_t reg;

    membar();
}
 
/** Read IMMU TLB Tag Read Register.
 *
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified IMMU TLB Tag Read Register.
 */
static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
{
    itlb_tag_read_addr_t tag;
 

    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
 *
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
 * @param entry     TLB Entry index.
 *
 * @return      Current value of specified DMMU TLB Tag Read Register.
 */
static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
{
    dtlb_tag_read_addr_t tag;
 

#endif
 
 
/** Write IMMU TLB Tag Access Register.
 *
 * @param v     Value to be written.
 */
static inline void itlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
    flush_pipeline();
}
 
/** Read IMMU TLB Tag Access Register.
 *
 * @return      Current value of IMMU TLB Tag Access Register.
 */
static inline uint64_t itlb_tag_access_read(void)
{
    return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
}
 
/** Write DMMU TLB Tag Access Register.
 *
 * @param v     Value to be written.
 */
static inline void dtlb_tag_access_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
    membar();
}
 
/** Read DMMU TLB Tag Access Register.
 *
 * @return      Current value of DMMU TLB Tag Access Register.
 */
static inline uint64_t dtlb_tag_access_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
}
 
 
/** Write IMMU TLB Data in Register.
 *
 * @param v     Value to be written.
 */
static inline void itlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
    flush_pipeline();
}
 
/** Write DMMU TLB Data in Register.
 *
 * @param v     Value to be written.
 */
static inline void dtlb_data_in_write(uint64_t v)
{
    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
    membar();
}
 
/** Read ITLB Synchronous Fault Status Register.
 *
 * @return      Current content of I-SFSR register.
 */
static inline uint64_t itlb_sfsr_read(void)
{
    return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
}
 
/** Write ITLB Synchronous Fault Status Register.
 *
 * @param v     New value of I-SFSR register.
 */
static inline void itlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
    flush_pipeline();
}
 
/** Read DTLB Synchronous Fault Status Register.
 *
 * @return      Current content of D-SFSR register.
 */
static inline uint64_t dtlb_sfsr_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
}
 
/** Write DTLB Synchronous Fault Status Register.
 *
 * @param v     New value of D-SFSR register.
 */
static inline void dtlb_sfsr_write(uint64_t v)
{
    asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
    membar();
}
 
/** Read DTLB Synchronous Fault Address Register.
 *
 * @return      Current content of D-SFAR register.
 */
static inline uint64_t dtlb_sfar_read(void)
{
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
}
 
/** Perform IMMU TLB Demap Operation.
 *
 
 * @param type      Selects between context and page demap (and entire MMU
 *          demap on US3).
 * @param context_encoding Specifies which Context register has Context ID for
 *          demap.
 * @param page      Address which is on the page to be demapped.
 */
static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
{
    tlb_demap_addr_t da;
    page_address_t pg;

   
    da.type = type;
    da.context = context_encoding;
    da.vpn = pg.vpn;
   
 
    /* da.value is the address within the ASI */
    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
 
    flush_pipeline();
}
 
/** Perform DMMU TLB Demap Operation.
 *
 
 * @param type      Selects between context and page demap (and entire MMU
 *          demap on US3).
 * @param context_encoding Specifies which Context register has Context ID for
 *          demap.
 * @param page      Address which is on the page to be demapped.
 */
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
{
    tlb_demap_addr_t da;
    page_address_t pg;

   
    da.type = type;
    da.context = context_encoding;
    da.vpn = pg.vpn;
   
 
    /* da.value is the address within the ASI */
    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
 
    membar();
}
 
extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
 
extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
 
extern void describe_mmu_fault(void);
 
#endif /* !def __ASM__ */
 
#endif
 

Rev 3743	Rev 3770
Line 44...	Line 44...
44	/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */	44	/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
45	#if defined (US3)	45	#if defined (US3)
46	#define DTLB_MAX_LOCKED_ENTRIES 16	46	#define DTLB_MAX_LOCKED_ENTRIES 16
47	#endif	47	#endif
48		48
-		49	#define MEM_CONTEXT_KERNEL 0
-		50	#define MEM_CONTEXT_TEMP 1
-		51
49	/** Bit width of the TLB-locked portion of kernel address space. */	52	/** Bit width of the TLB-locked portion of kernel address space. */
50	#define KERNEL_PAGE_WIDTH 22 /* 4M */	53	#define KERNEL_PAGE_WIDTH 22 /* 4M */
51		54
52	/* TLB Demap Operation types. */	55	/* TLB Demap Operation types. */
53	#define TLB_DEMAP_PAGE 0	56	#define TLB_DEMAP_PAGE 0
Line 89...	Line 92...
89	#include <arch/mm/page.h>	92	#include <arch/mm/page.h>
90	#include <arch/asm.h>	93	#include <arch/asm.h>
91	#include <arch/barrier.h>	94	#include <arch/barrier.h>
92	#include <arch/types.h>	95	#include <arch/types.h>
93	#include <arch/register.h>	96	#include <arch/register.h>
94	#include <arch/cpu.h>	97	#include <arch/sun4u/cpu.h>
95		98
96	union tlb_context_reg {	99	union tlb_context_reg {
97	uint64_t v;	100	uint64_t v;
98	struct {	101	struct {
99	unsigned long : 51;	102	unsigned long : 51;
Line 126...	Line 129...
126		129
127	/*	130	/*
128	* In US3, I-MMU and D-MMU have different formats of the data	131	* In US3, I-MMU and D-MMU have different formats of the data
129	* access register virtual address. In the corresponding	132	* access register virtual address. In the corresponding
130	* structures the member variable for the entry number is	133	* structures the member variable for the entry number is
131	* called "local_tlb_entry" - it contrast with the "tlb_entry"	134	* called "local_tlb_entry" - it contrasts with the "tlb_entry"
132	* for the US data access register VA structure. The rationale	135	* for the US data access register VA structure. The rationale
133	* behind this is to prevent careless mistakes in the code	136	* behind this is to prevent careless mistakes in the code
134	* caused by setting only the entry number and not the TLB	137	* caused by setting only the entry number and not the TLB
135	* number in the US3 code (when taking the code from US).	138	* number in the US3 code (when taking the code from US).
136	*/	139	*/
Line 228...	Line 231...
228	* Functions for determining the number of entries in TLBs. They either return	231	* Functions for determining the number of entries in TLBs. They either return
229	* a constant value or a value based on the CPU autodetection.	232	* a constant value or a value based on the CPU autodetection.
230	*/	233	*/
231		234
232	/**	235	/**
233	* Determine the number od entries in the DMMU's small TLB.	236	* Determine the number of entries in the DMMU's small TLB.
234	*/	237	*/
235	static inline uint16_t tlb_dsmall_size(void)	238	static inline uint16_t tlb_dsmall_size(void)
236	{	239	{
237	return 16;	240	return 16;
238	}	241	}
239		242
240	/**	243	/**
241	* Determine the number od entries in each DMMU's big TLB.	244	* Determine the number of entries in each DMMU's big TLB.
242	*/	245	*/
243	static inline uint16_t tlb_dbig_size(void)	246	static inline uint16_t tlb_dbig_size(void)
244	{	247	{
245	return 512;	248	return 512;
246	}	249	}
247		250
248	/**	251	/**
249	* Determine the number od entries in the IMMU's small TLB.	252	* Determine the number of entries in the IMMU's small TLB.
250	*/	253	*/
251	static inline uint16_t tlb_ismall_size(void)	254	static inline uint16_t tlb_ismall_size(void)
252	{	255	{
253	return 16;	256	return 16;
254	}	257	}
255		258
256	/**	259	/**
257	* Determine the number od entries in the IMMU's big TLB.	260	* Determine the number of entries in the IMMU's big TLB.
258	*/	261	*/
259	static inline uint16_t tlb_ibig_size(void)	262	static inline uint16_t tlb_ibig_size(void)
260	{	263	{
261	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)	264	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
262	return 512;	265	return 512;
Line 266...	Line 269...
266		269
267	#endif	270	#endif
268		271
269	/** Read MMU Primary Context Register.	272	/** Read MMU Primary Context Register.
270	*	273	*
271	* @return Current value of Primary Context Register.	274	* @return Current value of Primary Context Register.
272	*/	275	*/
273	static inline uint64_t mmu_primary_context_read(void)	276	static inline uint64_t mmu_primary_context_read(void)
274	{	277	{
275	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);	278	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
276	}	279	}
277		280
278	/** Write MMU Primary Context Register.	281	/** Write MMU Primary Context Register.
279	*	282	*
280	* @param v New value of Primary Context Register.	283	* @param v New value of Primary Context Register.
281	*/	284	*/
282	static inline void mmu_primary_context_write(uint64_t v)	285	static inline void mmu_primary_context_write(uint64_t v)
283	{	286	{
284	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);	287	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
285	flush_pipeline();	288	flush_pipeline();
286	}	289	}
287		290
288	/** Read MMU Secondary Context Register.	291	/** Read MMU Secondary Context Register.
289	*	292	*
290	* @return Current value of Secondary Context Register.	293	* @return Current value of Secondary Context Register.
291	*/	294	*/
292	static inline uint64_t mmu_secondary_context_read(void)	295	static inline uint64_t mmu_secondary_context_read(void)
293	{	296	{
294	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);	297	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
295	}	298	}
296		299
297	/** Write MMU Primary Context Register.	300	/** Write MMU Primary Context Register.
298	*	301	*
299	* @param v New value of Primary Context Register.	302	* @param v New value of Primary Context Register.
300	*/	303	*/
301	static inline void mmu_secondary_context_write(uint64_t v)	304	static inline void mmu_secondary_context_write(uint64_t v)
302	{	305	{
303	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);	306	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
304	flush_pipeline();	307	flush_pipeline();
Line 306...	Line 309...
306		309
307	#if defined (US)	310	#if defined (US)
308		311
309	/** Read IMMU TLB Data Access Register.	312	/** Read IMMU TLB Data Access Register.
310	*	313	*
311	* @param entry TLB Entry index.	314	* @param entry TLB Entry index.
312	*	315	*
313	* @return Current value of specified IMMU TLB Data Access Register.	316	* @return Current value of specified IMMU TLB Data Access
-		317	* Register.
314	*/	318	*/
315	static inline uint64_t itlb_data_access_read(index_t entry)	319	static inline uint64_t itlb_data_access_read(index_t entry)
316	{	320	{
317	itlb_data_access_addr_t reg;	321	itlb_data_access_addr_t reg;
318		322
Line 321...	Line 325...
321	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);	325	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
322	}	326	}
323		327
324	/** Write IMMU TLB Data Access Register.	328	/** Write IMMU TLB Data Access Register.
325	*	329	*
326	* @param entry TLB Entry index.	330	* @param entry TLB Entry index.
327	* @param value Value to be written.	331	* @param value Value to be written.
328	*/	332	*/
329	static inline void itlb_data_access_write(index_t entry, uint64_t value)	333	static inline void itlb_data_access_write(index_t entry, uint64_t value)
330	{	334	{
331	itlb_data_access_addr_t reg;	335	itlb_data_access_addr_t reg;
332		336
Line 336...	Line 340...
336	flush_pipeline();	340	flush_pipeline();
337	}	341	}
338		342
339	/** Read DMMU TLB Data Access Register.	343	/** Read DMMU TLB Data Access Register.
340	*	344	*
341	* @param entry TLB Entry index.	345	* @param entry TLB Entry index.
342	*	346	*
343	* @return Current value of specified DMMU TLB Data Access Register.	347	* @return Current value of specified DMMU TLB Data Access
-		348	* Register.
344	*/	349	*/
345	static inline uint64_t dtlb_data_access_read(index_t entry)	350	static inline uint64_t dtlb_data_access_read(index_t entry)
346	{	351	{
347	dtlb_data_access_addr_t reg;	352	dtlb_data_access_addr_t reg;
348		353
Line 351...	Line 356...
351	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);	356	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
352	}	357	}
353		358
354	/** Write DMMU TLB Data Access Register.	359	/** Write DMMU TLB Data Access Register.
355	*	360	*
356	* @param entry TLB Entry index.	361	* @param entry TLB Entry index.
357	* @param value Value to be written.	362	* @param value Value to be written.
358	*/	363	*/
359	static inline void dtlb_data_access_write(index_t entry, uint64_t value)	364	static inline void dtlb_data_access_write(index_t entry, uint64_t value)
360	{	365	{
361	dtlb_data_access_addr_t reg;	366	dtlb_data_access_addr_t reg;
362		367
Line 366...	Line 371...
366	membar();	371	membar();
367	}	372	}
368		373
369	/** Read IMMU TLB Tag Read Register.	374	/** Read IMMU TLB Tag Read Register.
370	*	375	*
371	* @param entry TLB Entry index.	376	* @param entry TLB Entry index.
372	*	377	*
373	* @return Current value of specified IMMU TLB Tag Read Register.	378	* @return Current value of specified IMMU TLB Tag Read Register.
374	*/	379	*/
375	static inline uint64_t itlb_tag_read_read(index_t entry)	380	static inline uint64_t itlb_tag_read_read(index_t entry)
376	{	381	{
377	itlb_tag_read_addr_t tag;	382	itlb_tag_read_addr_t tag;
378		383
Line 381...	Line 386...
381	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);	386	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
382	}	387	}
383		388
384	/** Read DMMU TLB Tag Read Register.	389	/** Read DMMU TLB Tag Read Register.
385	*	390	*
386	* @param entry TLB Entry index.	391	* @param entry TLB Entry index.
387	*	392	*
388	* @return Current value of specified DMMU TLB Tag Read Register.	393	* @return Current value of specified DMMU TLB Tag Read Register.
389	*/	394	*/
390	static inline uint64_t dtlb_tag_read_read(index_t entry)	395	static inline uint64_t dtlb_tag_read_read(index_t entry)
391	{	396	{
392	dtlb_tag_read_addr_t tag;	397	dtlb_tag_read_addr_t tag;
393		398
Line 399...	Line 404...
399	#elif defined (US3)	404	#elif defined (US3)
400		405
401		406
402	/** Read IMMU TLB Data Access Register.	407	/** Read IMMU TLB Data Access Register.
403	*	408	*
404	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)	409	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
405	* @param entry TLB Entry index.	410	* @param entry TLB Entry index.
406	*	411	*
407	* @return Current value of specified IMMU TLB Data Access Register.	412	* @return Current value of specified IMMU TLB Data Access
-		413	* Register.
408	*/	414	*/
409	static inline uint64_t itlb_data_access_read(int tlb, index_t entry)	415	static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
410	{	416	{
411	itlb_data_access_addr_t reg;	417	itlb_data_access_addr_t reg;
412		418
Line 415...	Line 421...
415	reg.local_tlb_entry = entry;	421	reg.local_tlb_entry = entry;
416	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);	422	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
417	}	423	}
418		424
419	/** Write IMMU TLB Data Access Register.	425	/** Write IMMU TLB Data Access Register.
420	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)	426	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
421	* @param entry TLB Entry index.	427	* @param entry TLB Entry index.
422	* @param value Value to be written.	428	* @param value Value to be written.
423	*/	429	*/
424	static inline void itlb_data_access_write(int tlb, index_t entry,	430	static inline void itlb_data_access_write(int tlb, index_t entry,
425	uint64_t value)	431	uint64_t value)
426	{	432	{
427	itlb_data_access_addr_t reg;	433	itlb_data_access_addr_t reg;
Line 433...	Line 439...
433	flush_pipeline();	439	flush_pipeline();
434	}	440	}
435		441
436	/** Read DMMU TLB Data Access Register.	442	/** Read DMMU TLB Data Access Register.
437	*	443	*
438	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)	444	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
439	* @param entry TLB Entry index.	445	* @param entry TLB Entry index.
440	*	446	*
441	* @return Current value of specified DMMU TLB Data Access Register.	447	* @return Current value of specified DMMU TLB Data Access
-		448	* Register.
442	*/	449	*/
443	static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)	450	static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
444	{	451	{
445	dtlb_data_access_addr_t reg;	452	dtlb_data_access_addr_t reg;
446		453
Line 450...	Line 457...
450	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);	457	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
451	}	458	}
452		459
453	/** Write DMMU TLB Data Access Register.	460	/** Write DMMU TLB Data Access Register.
454	*	461	*
455	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)	462	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
456	* @param entry TLB Entry index.	463	* @param entry TLB Entry index.
457	* @param value Value to be written.	464	* @param value Value to be written.
458	*/	465	*/
459	static inline void dtlb_data_access_write(int tlb, index_t entry,	466	static inline void dtlb_data_access_write(int tlb, index_t entry,
460	uint64_t value)	467	uint64_t value)
461	{	468	{
462	dtlb_data_access_addr_t reg;	469	dtlb_data_access_addr_t reg;
Line 468...	Line 475...
468	membar();	475	membar();
469	}	476	}
470		477
471	/** Read IMMU TLB Tag Read Register.	478	/** Read IMMU TLB Tag Read Register.
472	*	479	*
473	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)	480	* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
474	* @param entry TLB Entry index.	481	* @param entry TLB Entry index.
475	*	482	*
476	* @return Current value of specified IMMU TLB Tag Read Register.	483	* @return Current value of specified IMMU TLB Tag Read Register.
477	*/	484	*/
478	static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)	485	static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
479	{	486	{
480	itlb_tag_read_addr_t tag;	487	itlb_tag_read_addr_t tag;
481		488
Line 485...	Line 492...
485	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);	492	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
486	}	493	}
487		494
488	/** Read DMMU TLB Tag Read Register.	495	/** Read DMMU TLB Tag Read Register.
489	*	496	*
490	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)	497	* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
491	* @param entry TLB Entry index.	498	* @param entry TLB Entry index.
492	*	499	*
493	* @return Current value of specified DMMU TLB Tag Read Register.	500	* @return Current value of specified DMMU TLB Tag Read Register.
494	*/	501	*/
495	static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)	502	static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
496	{	503	{
497	dtlb_tag_read_addr_t tag;	504	dtlb_tag_read_addr_t tag;
498		505
Line 505...	Line 512...
505	#endif	512	#endif
506		513
507		514
508	/** Write IMMU TLB Tag Access Register.	515	/** Write IMMU TLB Tag Access Register.
509	*	516	*
510	* @param v Value to be written.	517	* @param v Value to be written.
511	*/	518	*/
512	static inline void itlb_tag_access_write(uint64_t v)	519	static inline void itlb_tag_access_write(uint64_t v)
513	{	520	{
514	asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);	521	asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
515	flush_pipeline();	522	flush_pipeline();
516	}	523	}
517		524
518	/** Read IMMU TLB Tag Access Register.	525	/** Read IMMU TLB Tag Access Register.
519	*	526	*
520	* @return Current value of IMMU TLB Tag Access Register.	527	* @return Current value of IMMU TLB Tag Access Register.
521	*/	528	*/
522	static inline uint64_t itlb_tag_access_read(void)	529	static inline uint64_t itlb_tag_access_read(void)
523	{	530	{
524	return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);	531	return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
525	}	532	}
526		533
527	/** Write DMMU TLB Tag Access Register.	534	/** Write DMMU TLB Tag Access Register.
528	*	535	*
529	* @param v Value to be written.	536	* @param v Value to be written.
530	*/	537	*/
531	static inline void dtlb_tag_access_write(uint64_t v)	538	static inline void dtlb_tag_access_write(uint64_t v)
532	{	539	{
533	asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);	540	asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
534	membar();	541	membar();
535	}	542	}
536		543
537	/** Read DMMU TLB Tag Access Register.	544	/** Read DMMU TLB Tag Access Register.
538	*	545	*
539	* @return Current value of DMMU TLB Tag Access Register.	546	* @return Current value of DMMU TLB Tag Access Register.
540	*/	547	*/
541	static inline uint64_t dtlb_tag_access_read(void)	548	static inline uint64_t dtlb_tag_access_read(void)
542	{	549	{
543	return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);	550	return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
544	}	551	}
545		552
546		553
547	/** Write IMMU TLB Data in Register.	554	/** Write IMMU TLB Data in Register.
548	*	555	*
549	* @param v Value to be written.	556	* @param v Value to be written.
550	*/	557	*/
551	static inline void itlb_data_in_write(uint64_t v)	558	static inline void itlb_data_in_write(uint64_t v)
552	{	559	{
553	asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);	560	asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
554	flush_pipeline();	561	flush_pipeline();
555	}	562	}
556		563
557	/** Write DMMU TLB Data in Register.	564	/** Write DMMU TLB Data in Register.
558	*	565	*
559	* @param v Value to be written.	566	* @param v Value to be written.
560	*/	567	*/
561	static inline void dtlb_data_in_write(uint64_t v)	568	static inline void dtlb_data_in_write(uint64_t v)
562	{	569	{
563	asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);	570	asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
564	membar();	571	membar();
565	}	572	}
566		573
567	/** Read ITLB Synchronous Fault Status Register.	574	/** Read ITLB Synchronous Fault Status Register.
568	*	575	*
569	* @return Current content of I-SFSR register.	576	* @return Current content of I-SFSR register.
570	*/	577	*/
571	static inline uint64_t itlb_sfsr_read(void)	578	static inline uint64_t itlb_sfsr_read(void)
572	{	579	{
573	return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);	580	return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
574	}	581	}
575		582
576	/** Write ITLB Synchronous Fault Status Register.	583	/** Write ITLB Synchronous Fault Status Register.
577	*	584	*
578	* @param v New value of I-SFSR register.	585	* @param v New value of I-SFSR register.
579	*/	586	*/
580	static inline void itlb_sfsr_write(uint64_t v)	587	static inline void itlb_sfsr_write(uint64_t v)
581	{	588	{
582	asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);	589	asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
583	flush_pipeline();	590	flush_pipeline();
584	}	591	}
585		592
586	/** Read DTLB Synchronous Fault Status Register.	593	/** Read DTLB Synchronous Fault Status Register.
587	*	594	*
588	* @return Current content of D-SFSR register.	595	* @return Current content of D-SFSR register.
589	*/	596	*/
590	static inline uint64_t dtlb_sfsr_read(void)	597	static inline uint64_t dtlb_sfsr_read(void)
591	{	598	{
592	return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);	599	return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
593	}	600	}
594		601
595	/** Write DTLB Synchronous Fault Status Register.	602	/** Write DTLB Synchronous Fault Status Register.
596	*	603	*
597	* @param v New value of D-SFSR register.	604	* @param v New value of D-SFSR register.
598	*/	605	*/
599	static inline void dtlb_sfsr_write(uint64_t v)	606	static inline void dtlb_sfsr_write(uint64_t v)
600	{	607	{
601	asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);	608	asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
602	membar();	609	membar();
603	}	610	}
604		611
605	/** Read DTLB Synchronous Fault Address Register.	612	/** Read DTLB Synchronous Fault Address Register.
606	*	613	*
607	* @return Current content of D-SFAR register.	614	* @return Current content of D-SFAR register.
608	*/	615	*/
609	static inline uint64_t dtlb_sfar_read(void)	616	static inline uint64_t dtlb_sfar_read(void)
610	{	617	{
611	return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);	618	return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
612	}	619	}
613		620
614	/** Perform IMMU TLB Demap Operation.	621	/** Perform IMMU TLB Demap Operation.
615	*	622	*
616	* @param type	-
617	* Selects between context and page demap	623	* @param type Selects between context and page demap (and entire MMU
618	* (and entire MMU demap on US3).	624	* demap on US3).
619	* @param context_encoding Specifies which Context register has Context ID for	625	* @param context_encoding Specifies which Context register has Context ID for
620	* demap.	626	* demap.
621	* @param page Address which is on the page to be demapped.	627	* @param page Address which is on the page to be demapped.
622	*/	628	*/
623	static inline void itlb_demap(int type, int context_encoding, uintptr_t page)	629	static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
624	{	630	{
625	tlb_demap_addr_t da;	631	tlb_demap_addr_t da;
626	page_address_t pg;	632	page_address_t pg;
Line 630...	Line 636...
630		636
631	da.type = type;	637	da.type = type;
632	da.context = context_encoding;	638	da.context = context_encoding;
633	da.vpn = pg.vpn;	639	da.vpn = pg.vpn;
634		640
635	asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the	-
636	* address within the	641	/* da.value is the address within the ASI */
637	* ASI */	642	asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
-		643
638	flush_pipeline();	644	flush_pipeline();
639	}	645	}
640		646
641	/** Perform DMMU TLB Demap Operation.	647	/** Perform DMMU TLB Demap Operation.
642	*	648	*
643	* @param type	-
644	* Selects between context and page demap	649	* @param type Selects between context and page demap (and entire MMU
645	* (and entire MMU demap on US3).	650	* demap on US3).
646	* @param context_encoding Specifies which Context register has Context ID for	651	* @param context_encoding Specifies which Context register has Context ID for
647	* demap.	652	* demap.
648	* @param page Address which is on the page to be demapped.	653	* @param page Address which is on the page to be demapped.
649	*/	654	*/
650	static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)	655	static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
651	{	656	{
652	tlb_demap_addr_t da;	657	tlb_demap_addr_t da;
653	page_address_t pg;	658	page_address_t pg;
Line 657...	Line 662...
657		662
658	da.type = type;	663	da.type = type;
659	da.context = context_encoding;	664	da.context = context_encoding;
660	da.vpn = pg.vpn;	665	da.vpn = pg.vpn;
661		666
662	asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the	-
663	* address within the	667	/* da.value is the address within the ASI */
664	* ASI */	668	asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
-		669
665	membar();	670	membar();
666	}	671	}
667		672
668	extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate);	673	extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
669	extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate);	674	extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
670	extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate);	675	extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
671		676
672	extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);	677	extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
673		678
674	extern void dump_sfsr_and_sfar(void);	679	extern void describe_mmu_fault(void);
675		680
676	#endif /* !def __ASM__ */	681	#endif /* !def __ASM__ */
677		682
678	#endif	683	#endif
679		684

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(root)/branches/sparc/kernel/arch/sparc64/include/mm/sun4u/tlb.h – Rev 3743 → 3770