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Rev 3549 Rev 3582
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	 */
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	 */
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	/*
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	/*
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	 * US3 processors have a write-invalidate cache, so explicitly
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	 * US3 processors have a write-invalidate cache, so explicitly
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	 * invalidating it is not required. Whether to invalidate I-cache
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	 * invalidating it is not required. Whether to invalidate I-cache
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	 * or not is decided according to the value of the ver.impl bits
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	 * or not is decided according to the value of the global
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	 * in the Version register.
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	 * "subarchitecture" variable (set in the bootstrap).
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	 */
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	 */
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! the lowest/greatest value of ver.impl for US3
 - 
 
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#define FIRST_US3_CPU 0x14
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	set subarchitecture, %g2
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#define LAST_US3_CPU 0x19
 - 
 
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	rdpr %ver, %g2			! autodetect CPU using the Version register
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	sllx %g2, 16, %g2		! extract ver.impl bits
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	srlx %g2, 48, %g2
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	ldub [%g2], %g2
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	addcc %g2, -FIRST_US3_CPU, %g0	! flush if ver.impl < FISRT_US3_CPU
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	bl 0f
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	nop
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	addcc %g2, -LAST_US3_CPU, %g0	! flush if ver.impl > LAST_US3_CPU
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	bg 0f
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	cmp %g2, 3
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	nop
 - 
 
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	ba 1f
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	be 1f
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	nop
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	nop
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0:
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0:
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	call icache_flush
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	call icache_flush
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	nop
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	nop
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1:
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1:
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- 
 
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	membar #StoreStore
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	membar #StoreStore
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	/*
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	/*
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	 * Flush the instruction pipeline.
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	 * Flush the instruction pipeline.
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	 */
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	 */